• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Korea Society of Computer and Information
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• v.14 no.1
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• pp.81-89
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• 2009

To support dynamic Region-of-Interest(ROI) in JPEG2000, a fast ROI mask generation is needed. In the existing methods of ROI coding, after scanning all the pixels in order and discriminating ROI, an ROI mask has been generated. Our method scans 4 pixels of the corners in one code block, and then based on those informations, scans the edges from the corners to get the boundaries of ROI and background. These informations are consisted of a distributed information of ROI and two coordinates of the pixels, which are the points the edges and the boundaries meet. These informations are transmitted to encoder and supported for fast ROI mask generation. There were no great differences between the proposed method and the existing methods in quality, but the proposed method showed superiority in speed.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.9
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• pp.327-336
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• 2015

Mobile game servers usually execute frequent dynamic memory allocation for generating the buffers that deal with clients requests. It causes to deteriorate the performance of game servers since it increases system workload and memory fragmentation. In this paper, we propose fixed-sized memory pool management method. Memory pool for the proposed method has a sequential memory structure based on circular linked list data structure. It solves memory fragmentation problem and saves time for searching the memory blocks which are required for memory allocation and deallocation. We showed the efficiency of the proposed method by evaluating the performance of dynamic memory allocation, through the proposed method and the memory pool management method based on boost open source library.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.148-155
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• 2014

In this research a signal processing system is designed for detecting the ultrasonic signal envelope using Xilinx's Zynq SoC(system on chip). As a design tool, Vivado IDE(integrated design environment) is used to hierarchically design the whole signal processing system. The proposed system consists of a Zynq-internal ADC, an FIR(finite impulse response) BPF(band pass filter), an absolute value calculator, an FIR LPF(lpw pass filter), and the Kalman filter. Under this configuration, two design schemes, HW design scheme with LPF as a final stage and HW/SW co-design scheme with a Kalman filter as a final stage, are compared in terms of the performance and efficiency. As a result, envelope detecting performances of the two schemes are proved to be almost same, but the HW/SW co-design is verified to be much more efficient than the HW design considering the much smaller time consumption during system design.

• Journal of the Korea Society of Computer and Information
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• v.16 no.12
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• pp.103-112
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• 2011

Motion estimation (ME) is regarded as an important component in a video encoding process, because it consumes a large computation complexity. H.264/AVC requires additional computation overheads for fractional search and interpolation. This causes a problem that computational complexity is increased. In Motion estimation, SATD(Sum of Transform Difference) has the characteristics of a parabolic based on the minimum point. In this paper, we propose new prediction algorithm to reduce search point in motion estimation by sub-pixel interpolation characteristics. The proposed algorithm reduces the time of encoding process by decreasing computational complexity. Experimental results show that the proposed method reduces 20% of the computation complexity of motion estimation, while the degradation in video quality is negligible.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.34-40
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• 2003

The paper presents a method to detect dissolve shots of video scene change detections in an MPEG compressed domain. The proposed algorithm uses color-R DCT coefficients of Ⅰ, P-frames for a fast operation and accurate detection and a minimum decoding process in MPEG sequences. The paper presents a method to detect dissolve shot for three-dimensional visualization and analysis of Image in order to recognize easily in computer as a human detects accurately shots of scene change. First, Color-R DCT coefficients for 8*8 units are obtained and the features are summed in a row. Second, Four-step analysis are Performed for differences of the sum in the frame sequences. The experimental results showed that the algorithm has better detection performance, such as precision and recall rate, than the existing method using an average for all DC image by performing four step analysis. The algorithm has the advantage of speed, simplicity and accuracy. In addition. it requires less amount of storage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.2
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• pp.151-157
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• 2022

In this paper, the performance of various blockchain consensus algorithms was compared and analyzed as a method to increase the transaction cost and processing time during NFT transactions and to increase the transaction stability requirements that occur during smart contract execution. Network reliability and TPS are evaluation items for performance comparison. TPS and the stability of the Consensus algorithm are presented for three evaluation items. In order to establish a standardized expression for each evaluation item, the reliability of the node and the success rate of the smart contract were considered as variables in the calculation formula, and the performance of the consensus algorithm of the three groups, PoW/PoS, Paxos/Raft and PBFT, was compared under the same conditions. / analyzed. As a result of the performance evaluation, the network reliability of the three groups was similar, and in the case of the remaining two evaluation items, it was analyzed that the PBFT consensus algorithm was superior to other consensus algorithms. Through the performance evaluation equations and results of this study, it was analyzed that when the PBFT consensus processing process is reflected in the consensus process, the network reliability can be guaranteed and the stability and economic efficiency of the consensus algorithm can be increased.

• The Magazine of the IEIE
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• v.30 no.5
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• pp.95-95
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• 2003

현재의 라우팅 프로토콜은 다양한 사용자 요구를 만족시켜주기 위해서는 네트워크의 처리량을 최대화하고 동시에 사용자의 요구 시 QoS를 보장해주는 기법이 요구되고 있다. 기존의 최단경로 라우팅 프로토콜은 단일경로 라우팅으로 인해 병목현상의 단점을 지니고 있다. 즉, 원천과 목적지간 최단경로는 낮은 활용도를 나타내는 경로들이 많이 존재하지만 단일경로를 선택하므로서 폭주(congestion)의 발생확률이 높다. 최근에 들어 사용자의 QoS 요구 시, 다양한 QoS를 패킷 네트워크에서 처리할 수 있도록 IETF에서 DiffServ, RSVP, MPLS 등과 같은 패킷 QoS 기법에 대한 표준화 작업이 진행중이며, 그 중에서 Diffserv 네트워크가 대표적이다. 따라서 본 논문에서는 이 DiffServ 네트워크상에서 다양하게 유입되는 트래픽의 종류에 따라 사용자의 응용에 적절히 대응하여 트래픽을 처리하는 라우팅 기법 및 알고리즘을 연구하고 기존의 최선형 (Best effort) 트래픽을 처리하기 위한 트래픽 분산 라우팅 프로토콜 (Traffic-Balanced Rout-ing Protocol''TBRP)을 제안하였으며, 최적의 중간 노드를 선택하여 높은 순위의 상호형 데이터를 처리하기 위한 계층적 라우팅 프로토콜(또ierarchicalTra(fic-Scheduling Routing Protocol : HTSRP)을 연구하였다. 본 연구에서 제시한 프로토콜은 유, 무선망의 통합에 따른 다양한 엑세스망과 백본망에 유연한 트래픽 처리기법으로서 계층적 라우팅 알고리즘으로 적합하였다. 본 실험에서는 사용자의 QoS요청 시 제공되는 상호형 또는 스트리 밍 데이터를 위한 HTSRP_Q(Hierarchical Traffic-Scheduling Routing Pro-tocol for QoS)에 대해 성능이 우수함을 입증하였으며, 각 엑세스 단에서 요청하는 QoS 파라미터에 따라 자원을 최적화하여 QoS를 보장하고, 특히 지연에 민감한 트래픽을 처리하였으며, 제안한 프로토콜을 이용하여 사용자 요구 트래픽 종류에 따라 대화형 클래스, 스트리밍 클래스, 높은 순위의 상호형 클래스, 낮은 순위의 상호형 클래스, 그리고 background 클래스등 5개의 서비스 클래스로 분리하여 트래픽 특성에 맞게 처리할 수 있었다. QoS 관련 실험에서는 QoS 요청데이터를 균등하게 1에서 10Mbps 사이에 분포하였고 연결된 호에 대한 지속시간은 5분으로 하였다. 이러한 환경에서 프로토콜을 MaRS에 의해 실험을 하였고 기존의 거리-벡터 라우팅과 링크-상태 라우팅 프로토콜과 비교해서 처리량, 메시지 손실, 블럭킹율 등에서 비교적 우위의 성능을 확인할 수 있었으며, 특히, 차별화된 서비스의 특성에 맞게 라우팅 기법을 적용하므로서 망의 효율성과 안정성을 꾀할 수가 있었다. 연결 수 대 처리량에서는 HTSRP 프로토콜이 연결이 적을 때 DVR, LSR보다 우월하였으며 특히, 선형을 유지하였다. 연결 수 대 패킷 손실에서 HTSRP프로토콜에서 메시지 손실은 연결의 수가 낮거나 높을 때 다른 DVR과 LSR 라우팅 프로토콜과 유사한 결과를 나타내었다. Hotspo에서 TBRP, HTSRP프로토콜은 hotspot 연결의 수가 9일 때까지 DVR, LSR 보다 좋은 처리량를 나타냈고 HTSRP는 연결의 수가 6 이상일 때 가장 높은 처리량을 나타내었다. 일반 트래픽과 QoS 트래픽이 흔재할 경우는 트래픽이 증가할수록 HTSRP_Q가 가장 월등하였으며 , 로드가 증가할수록 낮은 블록킹률을 나타내었다. 본 논문에서는 점대점 전송을 기반으로 하였다. 앞으로 다양한 응용 S/W는 멀티캐스트 기반이 예상되므로 멀티캐스트 라우팅에 대한 연구가 필요하다. 본 논문의 프로토콜은 원천과 목적지간의 최단경로가 폭주상태가 아닌 해당 중간 노드를 이용한다. 최단경로의 모든 링크상의 트래픽 부하가 낮을 때 중간노드의 사용은 지연을 증가시킨다. 향후 최적의 성능을 위해 보완이 필요하다. 아울러, 2계위에서는 일반 트래픽과 QoS 트래픽이 혼재할 때 자동으로 네트워크의 효율적을 고려한 방법 선택이 필요하다.