• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.196-201
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• 2013

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1609-1617
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• 2000

In this paper a design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then subround is executed for one clock. To improve clock frequency online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. Also to eliminate performance degradation due to data input and data output time between host computer and coprocesor, background input/output method is used. The cryptographic coprocessor is designed using $0.25{\mu}{\textrm}{m}$ CMOS technology and consists of about 29,300 gates. Its peak performance is about 237 Mbps encryption or decryption rate under 100 Mhz clock frequncy and ECB mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.189-192
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• 2005

In this paper, we present a Petri Net (PN) model for reliability analysis of a shared database system. The system consists of components; a database, two processors, two memory and a bus. The database should be operational and at least one of the component should be also operational. Otherwise system will be down. Each component can be failed and repaired individually. Stochastic Reward Net (SRN) Model for reliability analysis is developed. SRN is potential to define various reward function and can be easily used to obtain performance measures. The modeling techniques using variable cardinality, enabling function, timed transition priority in SRN are shown.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1207-1212
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• 2011

This paper presents a study on the DSP(Digital Signal Processor) controller for the PBW(power-by-wire) system using BLDC(Brushless Direct Current) servo motor pump. The PBW hydraulic actuator was realized with hydraulic pump driven by BLDC servo motor, hydraulic cylinder and controller. This PBW system needs speed control of servo motor for linear thrust action of hydraulic cylinder. This paper implements a servo controller with vector control algorithm and MIN-MAX PWM technique. As CPU of a controller, TMS320F2812 DSP was adopted because it has PWM waveform generator, A/D converter, SPI(Serial Peripheral Interface) port and many input/output port etc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.576-585
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• 2014

Collecting and utilizing have a huge amount of personal data have caused severe security issues such as leakage of personal information. Several encryption algorithms for collected personal information have been widely adopted to prevent such problems. In this paper, a novel algorithm based on MapReduce is proposed for encrypting such private information. Furthermore, test environment has been built for the performance verification of the distributed encryption processing method. As the result of the test, average time efficiency has improved to 15.3% compare to encryption processing of token server and 3.13% compare to parallel processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6A
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• pp.885-892
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• 2000

A multi-used detector(MUD) using a radial basis function(RBF) network is proposed in a multicarrier-code division multiple access (MC-CDMA) system. In the proposed scheme, a RBF network is connected to the frequency domain in order to effectively utilize the frequency diversity. Simulations have been performed over the frequency selective and multipath fading channel. From these simulations, the proposed receiver is verified to be used for making the performance improvement in combating near-far effects and increasing the number of active users. The system capacity is increaed about 1.8 times at a BER of $10^{-3}$ under a single cell when the proposed scheme is compared with MUD using a parallel interference canceller(PIC).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.12
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• pp.1122-1132
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• 2012

Compressed sensing has been applied to many fields such as images, speech signals, radars, etc. It has been mainly applied to stationary signals, and reconstruction error could grow as compression ratios are increased by decreasing measurements. To resolve the problem, speech signals are divided into frames and processed in parallel. The frames are made sparse by dictionary learning, and adaptive compressed sensing is applied which designs the compressed sensing reconstruction matrix adaptively by using the difference between the sparse coefficient vector and its reconstruction. Through the proposed method, we could see that fast and accurate reconstruction of non-stationary signals is possible with compressed sensing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.682-684
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• 2004

The effect of 1/f noise by the random telegraph signal(RTS) on the phase noise and the jitter of CMOS ring Oscillator is investigated. 10 parallel piece-wise-linear current sources connected to each node model the RTS signals. The In, the power spectral density and the jitter of output of the ring oscillator are simulated as functions of the amplitude and time constant of RTS current source. It is confirmed that the increase of amplitude of RTS is directly related to the increase of the width of phase noise md the value of jitter. The shorter the time constant is, the wider width of FET peak and the larger value of cycle to cycle jitter are.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.