• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.165-173
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• 2023

In this paper, we propose an optimal implementation of lightweight block ciphers, SIMECK and SIMON counter operation mode, on a 32-bit RISC-V processor. Utilizing the characteristics of the CTR operating mode, we propose round function optimization that precomputes some values, single plaintext optimization and two plaintext parallel optimization. Since there are no previous research results on SIMECK and SIMON on RISC-V, we compared the performance of implementations with and without precomputation techniques for single plaintext optimization and two plaintext parallel optimization implementations. As a result, the implementations to which the precomputation technique was applied showed a performance improvement of 1% compared to the implementations to which precomputation was not applied.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.373-382
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• 2000

This paper is concerned with development of a communication module of POFS(Parallel Operating File System), which is the parallel file system to be operated on SPAX computer. SPAX is multiprocessor computer with clustering SMP architecture and being developed by ETRI. The operating system for SPAX is MISIX based on the Chorus microkernel. POFS has client/server architecture basically so that it is important to design a communication module. The communication module is so easily affected by network environment that bad design is the major reason that decreases the portability and performance of the parallel file system. This paper describes the structure and performance of the communication of the POFS. the theme is issued in the course of designing and developing POFS. The communication module of POFS was designed to support the portability and the architecture of parallel file system.

• KIPS Transactions on Software and Data Engineering
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• v.5 no.5
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• pp.231-242
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• 2016

In order to meet rapid changes of Web information, it is necessary to extend the current Web technologies to represent both the valid time and location of each fact and knowledge, and reason their relationships. Until recently, many researches on qualitative temporal reasoning have been conducted in laboratory-scale, dealing with small knowledge bases. However, in this paper, we propose the design and implementation of a parallel qualitative temporal reasoner, MRQUTER, which can make reasoning over Web-scale large knowledge bases. This parallel temporal reasoner was built on a Hadoop cluster system using the MapReduce parallel programming framework. It decomposes the entire qualitative temporal reasoning process into several MapReduce jobs such as the encoding and decoding job, the inverse and equal reasoning job, the transitive reasoning job, the refining job, and applies some optimization techniques into each component reasoning job implemented with a pair of Map and Reduce functions. Through experiments using large benchmarking temporal knowledge bases, MRQUTER shows high reasoning performance and scalability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.71-78
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• 2005

In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

• Journal of Satellite, Information and Communications
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• v.10 no.1
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• pp.1-5
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• 2015

With the help of fast growing multimedia technology and high preference for users of large screens, the newest video coding standard, HEVC (High Efficiency Video Coding) high-quality video compression), has been introduced. Therefore, the high definition image services which are four times more clear than conventional HD video, are getting popular. JPEG 2000 also has stated to support 4K and 8K UHD. As a result, it requires fast processing technology to read and write UHD images. This paper introduces a study on fast parallel processing technology for UHD images. For this purpose, first, JPEG 2000 is reviewed and a GPU based parallel implementation is proposed for a preprocessing of color conversion stage. The parallelled algorithm is implemented with OpenCL (Open Computing Language). The simulation results show that the proposed method shows 5 times performance improvements on processing speed for 4K UHD over the method using threads.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.400-408
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• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.9-16
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• 2011

GPU computing is emerging in high performance application area since it can easily exploit massive parallelism in a way of cost-effective computing. The power method which finds the eigen vector of a given matrix is widely used in various applications such as PageRank for calculating importance of web pages. In this research we made the power method efficiently parallelized on GPU and also suggested how it can be improved to enhance its performance. The power method mainly consists of matrix-vector product and it can be easily parallelized. However, it should decide the convergence of the eigen vector and need scaling of the vector subsequently. Such operations incur several calls to GPU kernels and data movement between host and GPU memories. We improved the performance of the power method by means of reduced calls to GPU kernels, optimized thread allocation and enhanced decision operation for the convergence.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Journal of the Korea Society of Computer and Information
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• v.18 no.1
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• pp.1-10
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• 2013

In this paper, we propose a CUDA(Common Unified Device Architecture) based SW(software) design method for CPU(Central Processing Unit) and GPU(Graphic Processing Unit) parallel structure to implement real-time process in 3D Laser ladar(LADAR) imaging system. LADAR is a complex system to generate 3-dimensional image based on the laser ranging information, and requires massive process resources in each phase. Therefore, designing and implementing parallel structure are crucial to realize a real-time process within limited system resource. As a conclusion, we can meet the speed of required real-time process allocating separable work load to CUDA GPU by analyzing process algorithm in each phase and confirm the process speed increase by 46%.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.765-774
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• 2001

In this paper, we proposed the striping policy for the storage nodes in the Linux-based parallel media stream server. We newly developed a storage clustering architecture, and named it as a system RAID architecture. In this system, many storage cluster nodes are grouped to operate as a single server. This system uses unique striping policy to distribute multimedia files into the parallel storage nodes. If a service request occurs, each storage cluster node transmits striped files concurrently to the clients. This scheme can provide the fair distribution of the preprocessing load in all storage cluster nodes. The feature of this system is a relative striping policy based on the file types, service types, and the number of storage nodes to provide the best service.