• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.101-102
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• 2013

CAN통신은 자동차 내부 전자제어장치 간의 통신을 위하여 개발되었으며, CAN통신은 UART 방식과는 달리 전송속도와 안정성 측면에서도 뛰어나고 배선 결선에서도 간편한 버스타입으로 구성할 수 있어서 배선량을 줄일 수 있어 생산시간의 단축과 신뢰성을 높일 수 있다. 최근에는 자동제동장치, 선박의 엔진제어 등 다양한 분야에서 사용되고 있다. 본 논문에서는 CAN통신을 기반으로 하여 3개의 리니어 액추에이터(Linear Actuator)를 통하여 수평 플랜트에 대한 수평제어를 구현하였다. 또한 본 논문의 수평제어시스템은 수평조절을 하는 액추에이터와 CAN통신을 내장한 AT90CAN128로 구성되어 있다. CAN통신을 기반의 수평제어를 통해 선박이나 자동차의 액추에이터를 조절하여 수평을 제어하고자 한다.

• Journal of the Korean Solar Energy Society
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• v.38 no.4
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• pp.33-42
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• 2018

In the application of the BIPV system, it is expected that the workability is lowered due to the difficulty in securing the space for wiring in the frame and the performance of the frame due to the wiring hole processing is lowered. Therefore, In this study, we propose a method to improve the wiring of the inner space of the BIPV frame, and through the simulation evaluation process, the thermal and condensation performance are secured by complementing the problems caused by the hole machining, and the time and effort required for BIPV construction are reduced. For this purpose, a wiring treatment method using a flange insertion tube was proposed, and the thermal and condensation performance was evaluated through simulation analysis.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.2
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• pp.31-43
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• 2019

In this study, polymer elastic bumps were fabricated for the flexible electronic package flip chip bonding and the viscoelastic and viscoplastic behavior of the polymer elastic bumps according to the temperature and load were analyzed using FEM and experiments. The polymer elastic bump is easy to deform by the bonding load, and it is confirmed that the bump height flatness problem is easily compensated and the stress concentration on thin chip is reduced remarkably. We also develop a spiral cap type and spoke cap type polymer elastic bump of $200{\mu}m$ diameter to complement Au metal cap crack phenomenon caused by excessive deformation of polymer elastic bump. The proposed polymer elastic bumps could reduce stress of metal wiring during bump deformation compared to metal cap bump, which is completely covered with metal wiring because the metal wiring on these bumps is partially patterned and easily deformable pattern. The spoke cap bump shows the lowest stress concentration in the metal wiring while maintaining the low contact resistance because the contact area between bump and pad was wider than that of the spiral cap bump.

• Proceedings of the Korea Institute of Fire Science and Engineering Conference
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• 2002.11a
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• pp.269-272
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• 2002

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.2
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• pp.316-316
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• 1997

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.68-74
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• 1985

In this Paper, we present a non-doglegging channel routing system for If layout using standard cells. This system produces a final two-layer wiring pattern in the horizontal track between two rows, each of which is a linear placement of standard cells of identical heights, satisfying the given net list specification. The layout of CMOS cell library Including nine primitive cells used in this paper is represented in CIF (Caltech Intermediate Form) using λ(Lambda) of 2 microns in Mead-Conway layout representation scheme. The cell dimension and 1/0 characteristics such as name, position and layer type of the pins are stored in Component Library to be used in the channel routing progranl, CROUT. 4 subprogram, NET-PLOT, was used to report a schemdtic layout result, and another subprogram, NETCIF was used to with a full-fledged final layout representation in GIF, A test run for realizing a dynamicmaster-slave D flip-flop with set/reset using primitive cells was shown to take 4 CPU seconds on VAX 11/780.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.877-887
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• 2015

In this paper, a design of communication joint tools to implement a legacy-line communication (LLC) system, which exploits various conductive lines in a train, is presented. We develop two kinds of joint tools; one is a conductive joint tool (CJT) that is connected directly to the conventional lines and the other is the inductive joint tool (IJT) which connects the conventional lines indirectly using electromagnetic induction. As a result, the practical experiment of data communication confirms that an LLC system with the developed joint tools has a transmission rate more than 20 Mbps in the distance of 200 m away. In addition, an environmental durability test shows that the joint tools operate stably in an extreme environmenal variation. It is, therefore, considered that the developed joint tools are very useful to implement a communication network in the train working currently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.18-24
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• 2007

As VLSI technology scales to nano-meter order, relatively increasing global wire-delay has added complexity to system design. Global wire-delay could be reduced by inserting pipeline-elements onto wire but it should be coupled with LIP(Latency Intensive Protocol) to have correct system timing. This combination however, drops the throughput although it ensures system functionality. In this paper, we propose a computation method useful for minimizing throughput deterioration when pipeline-elements are inserted to reduce global wire-delay. We apply this method while placing blocks in the floorplanning stage. When the necessary for this computation is reflected on the floorplanning cost function, the throughput increases by 16.97% on the average when compared with the floorplanning that uses the conventional heuristic throughput-evaluation-method.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.6
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• pp.11-16
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• 2021

In this paper, a quality inspection system was developed to identify the defective assembly of connectors used in automobile wiring. For waterproof connectors, an internal seal must be inserted for waterproofing. However, there are cases where it is omitted or double-inserted during production. An automatic inspection jig was designed using photosensors and touch switches to classify good and bad connector components. In the case of the existing visual inspection, 6,400 connectors were inspected when 5 people inspected for 8 hours. However, when using the inspection jig developed under the same conditions, 20,000 pieces were inspected. In other words, the productivity is greatly improved compared to the conventional visual inspection.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.