• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

• Journal of Korean Society of Transportation
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• v.23 no.8 s.86
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• pp.113-128
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• 2005

We propose a modified version of 'a Lazy Version of Eppstein's k shortest paths Algorithm(LVEA)' which can find the k shortest paths in total time O(m+ n log n+ K log K) in the worst-case. The algorithm we propose, since the Link repeated paths are all eliminated when enumerating k shortest paths, is No link repeated paths algorithm that is suitable in a transportation network.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.4
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• pp.31-41
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• 2016

This paper is to evaluate the performance of a proposed hybrid genetic algorithm (pro-HGA) approach using closed-loop supply chain (CLSC) model. The proposed CLSC model is a integrated supply chain network model both with forward logistics and reverse logistics. In the proposed CLSC model, the reuse, resale and waste disposal using the returned products are taken into consideration. For implementing the proposed CLSC model, two conventional approaches and the pro-HGA are used in numerical experiment and their performances are compared with each other using various measures of performance. The experimental results show that the pro-HGA approach is more efficient in locating optimal solution than the other competing approaches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.564-566
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• 2003

전력 계통에서 안정한 전력을 공급하는 것은 매우 중요하다. 전력 계통의 오류는 전압 및 주파수를 감시함으로써 검출 가능하다. 본 논문에서는 디지털 위상 고정 루프를 이용한 전력 계통의 주파수 측정 장치를 제안하고 이를 구현한 결과를 제시하고자 한다. 제안한 주파수 측정 장치는 위상 고정 루프의 기본요소로 구성된다. 위상분별기는 배타적 논리연산을 통해 위상오차를 검출하고 위상의 앞섬 및 뒤짐의 검출이 가능하도록 설계하였으며, 전력 계통의 주파수 동특성을 고려해서 3차의 루프 필터를 설계하였다. DCO는 출력 주파수의 분해능을 고려하여 입력 신호를 정확하게 추정할 수 있도록 설계하였다. 제안한 주파수 측정 장치의 성능을 검증하기 위하여 모의실험을 통해 주파수 변동량의 측정 범위 및 정확도를 검토하였으며, FPGA와 CPU를 포함하는 하드웨어를 구현하였다. FPGA에는 Verilog HDL로 디지털 위상 고정 루프의 위상분별기와 DCO를 구현하였으며 루프필터는 소프트웨어로 구현하였다. 제안한 디지털 위상 고정 루프의 성능 검증을 위해 정밀한 함수 발생기의 출력을 인가한 후 출력 주파수를 측정한 결과 및 전력 계통에 대한 실험 결과를 제시하였다.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1823-1825
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• 2001

고리형 반도체-광섬유 레이저 공진기 안에 높은 복굴절률을 가지고 있는 편광 유지 광섬유 루프 거울을 삽입하여 새로운 구조의 다파장 발진 시스템을 제안하고 구현하였다. 이득 매질인 반도체 광 증폭기의 특성으로 인해 실온에서 파장 간격이 1 nm 이내인 22 개의 파장의 빛을 발진시킬 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.2
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• pp.27-36
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• 1998

통신시스템의 고발열 전자부품 냉각을 위해 3종류의 써모싸이폰을 각각의 용도에 따라 개 발하였으며 그 각각의 설계변수에 대한 냉각특성을 실험적으로 구하였다. TS-I에서는 증발부 내부 에 금속스크린 메쉬형심지를 삽입함으로써 시간에 따른 온도 변화를 작게 하여 냉각성능 안정성을 확보하였고, TS-II에서는 9W/cm2의 높은 냉각성능을 가진 루프형 써모사이폰을 개발하였으며 TS-III에서는 작동유체의 종류, 파이프개수 와이어 삽입여부등 써모사이폰의 주요 설계변수에 따 른 냉각특성을 구하였다.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.37 no.4
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• pp.259-265
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• 2024

Shape memory alloy (SMA)-textile actuators have attracted significant attention across various fields, including soft robotics and wearable technology. These smooth actuators are developed by combining SMA and simple textile fibers and then knitting them into two loop patterns known as the knit (K-loop) and plain (P-loop) patterns. Both loops are distinguished by opposite bending characteristics owing to loop head geometry. However, the knitting processes for these actuator sheets require expertise and time, resulting in high production costs for knitted loop actuation sheets. This study introduces a novel method by which to assess the strain in SMA textile-based actuators, which experience large deformations when subjected to voltage. Owing to the highly nonlinear constitutive equations of the SMA material, developing an analytical model for numerical analysis is challenging. Therefore, this study employs a novel approach that utilizes a linear constitutive equation to analyze large deformations in SMA material with nonlinear geometry considerations. The user-defined material (UMAT) subroutine integrates the linear constitutive equation into the ABAQUS software suite. This equivalent unit cell (EUC) model is validated by comparing the experimental bending actuation results of K-loops and P-loops.