• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.6 s.312
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• pp.40-47
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• 2006

This paper introduces an efficient CRC logic partitioning algorithm to design pipelined parallel CRC circuits aimed at improving speed performance. Focusing on the cases that the input data width is greater than the polynomial degree, equations are derived to divide the parallel CRC logic and decide the length of the pipeline stage. Through design experiments on different types of parallel CRC circuits, we have found a significant reduction in delay by adopting our approach.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.205-208
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• 2005

본 논문에서는 IEEE 802.11a 무선 랜에서 burst error에 대한 에러 정정 코드로 사용되는 블록 인터리버의 설계방법을 제안한다. 블록 인터리버 메모리는 읽기 쓰기의 주소가 다르기 때문에 주소생성을 하기 위한 회로가 복잡해진다. 본 논문에서 제안하는 방법은 블록 인터리버의 설계에서 사용되는 $16{\times}18$ 크기의 메모리를 세분화하여 데이터를 읽어 들일 때 쓰이는 롬이나 복잡한 로직을 제거하거나 메모리 선택기를 추가하여 보다 간소화된 주소 생성 모듈을 설계하여 로직의 효율을 높인다.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.127-129
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• 2008

This paper describes a method of approximate reasoning for fuzzy control of servo system, based on decomposition of -level fuzzy sets. It is propose that logic circuits for fuzzy PI+PD are a body from fuzzy inference to defuzzificaion in cases where the output variable u directly is generated PWM. The effectiveness for robust and faster response of the fuzzy control scheme is verified for a variable parameter by comparison with a PID control and fuzzy control. A position control of DC servo system with a fuzzy logic controller successfully demonstrated.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.59-69
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• 2011

Since power analysis attack which uses a characteristic that power consumed by crypto device depends on processed data has been proposed, many logics that can block these correlation originally have been developed. DRP logic has been adopted by most of logics maintains power consumption balanced and reduces correlation between processed data and power consumption. However, semi-custom design is necessary because recently design circuits become more complex than before. This design method causes unbalanced design pattern that makes DRP logic consumes unbalanced power consumption which is vulnerable to power analysis attack. In this paper, we have developed new logic style which adds another discharge phase to discharge two output nodes at the same time based on DyCML to remove this unbalanced power consumption. Also, we simulated 1bit fulladder to compare proposed logic with other logics to prove improved performance. As a result, proposed logic is improved NED and NSD to 60% and power consumption reduces about 55% than any other logics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.317-326
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• 2016

In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.24-30
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• 2007

Latching optical switches and optical logic gates with AND or OR, and the INVERT functionality are demonstrated, for the first time, by the monolithic integration of a differential typed vertical cavity laser with depleted optical thyristor (VCL-DOT) structure with a low threshold current of 0.65 mA, a high slope efficiency of 0.38 mW/mA, and high sensitivity to input optical light. Many kinds of logic functions (AND, OR, NAND, NOR, and INVERT) are experimentally demonstrated using a differential switching operation scheme changing the intensity of a reference input beam without any changes of electrical circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.571-574
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• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.10
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• pp.291-298
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• 2020

The power generation of a PV system changes according to the weather variables, such as solar radiation and temperature. In particular, the output characteristics of photovoltaic systems, which are sensitive to changes in solar radiation, can be produced effectively and reliably in various weather conditions through MPPT (Maximum Power Point Tracking) control. This paper proposes a fuzzy-based MPPT control method to improve the efficiency and stability of the power production from a solar system. To verify the performance of the proposed method, under the same weather environment, the efficiency and stability of the newly proposed fuzzy logic were compared and evaluated empirically with P&O (Perturb and Observe), a representative algorithm of MPPT control. Furthermore, the circuits designed to improve the reliability and reliability of the hardware were manufactured from Printed Circuit Boards (PCB) to conduct experiments. Based on the results of the experiment during a certain period, the fuzzy-based MPPT proposed in this paper improved the efficiency by more than 4.4% compared to the MPPT based on the existing P&O algorithm and decreased the fluctuation width by more than 39.7% at the maximum power point.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.226-228
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• 2004

Twofish 알고리즘은 작은 부피의 로직, Triple-DES보다 강력한 암호화 레벨, 암호화 속도 등율 갖추어 모듈 설계 알고리즘으로 선정하였다. Twofish 알고리즘은 bitwired-XOR, Permutation, S-box, MDS, PHT를 걸치는 H함수를 각기 다른 키로 반복 라운드를 함으로써 대상 데이타를 암호화한다. 64~256bit의 키 크기와 라운딩 횟수를 조정하여 모듈의 부피나 처리속도를 유동성 있게 조절할 수 있는 장점이 있다. 하드웨어 기기와 응용에 사용하기 위하여 VHDL 모듈로 알고리즘을 설계하고 그 동작을 검증하였다. 구현된 회로는 기존의 방법에 비하여 파이프라인 단계를 적용함으로써 약 23%의 속도 향상을 얻을 수 있었다.