Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Design of Pipelined Parallel CRC Circuits

파이프라인 구조를 적용한 병렬 CRC 회로 설계

  • Yi, Hyun-Bean (Dept. of Computer Science & Engineering, Hanyang University) ;
  • Kim, Ki-Tae (Dept. of Computer Science & Engineering, Hanyang University) ;
  • Kwon, Young-Min (Dept. of Intelligent IT System Research Center, Korea Electronics Technology Institute) ;
  • Park, Sung-Ju (Dept. of Electronical Engineering Computer Science, Hanyang University)
  • 이현빈 (한양대학교 컴퓨터공학과) ;
  • 김기태 (한양대학교 컴퓨터공학과) ;
  • 권영민 (한국전자부품연구원 지능형 정보시스템 연구 센터) ;
  • 박성주 (한양대학교 전자컴퓨터공학과)
  • Published : 2006.11.25
Download PDF
⟨ Previous Next ⟩

Abstract

This paper introduces an efficient CRC logic partitioning algorithm to design pipelined parallel CRC circuits aimed at improving speed performance. Focusing on the cases that the input data width is greater than the polynomial degree, equations are derived to divide the parallel CRC logic and decide the length of the pipeline stage. Through design experiments on different types of parallel CRC circuits, we have found a significant reduction in delay by adopting our approach.

본 논문은 CRC 회로의 성능을 향상시키기 위하여 파이프라인 구조를 적용한 병렬 CRC 회로 설계 방법을 제시한다. 입력 데이터의 폭이 CRC 다항식의 차수보다 큰 병렬 CRC 회로를 파이프라인 구조로 변형하기 위하여 로직을 분할하고 파이프라인 단계의 길이를 결정하고, 각 파이프라인 단계에 레지스터를 삽입하는 알고리즘을 제시한다. 여러 가지 타입의 병렬 CRC 회로에 대해, 본 논문에서 제안한 방식이 현저하게 성능을 향상 시켰음을 알 수 있다.

Keywords

References

  1. D. V. Sarwate, 'Computation of Cyclic Redundancy Checks via Table Look-Up,' Comm. ACM, Aug. 1988 https://doi.org/10.1145/63030.63037
  2. S.M. Joshi, P.K. Dubey and M.A. Kaplan, 'A New Parallel Algorithm for CRC Generation,' IEEE International Conference on Communications, Vol. 3, pp. 18-22, Jun. 2000 https://doi.org/10.1109/ICC.2000.853801
  3. T.B. Pei and C. Zukowski, 'High-Speed Parallel CRC Circuits in VLSI,' IEEE Transaction on Communications, Vol. 40, no. 4, pp. 653-657, 1992 https://doi.org/10.1109/26.141415
  4. R.F. Hobson and K.L. Cheng, 'A High-Performance CMOS 32-Bit Parallel CRC Engine,' IEEE Journal of Solid-State Circuits, Vol. 34, No.2, pp. 233-235, Feb. 1999 https://doi.org/10.1109/4.743785
  5. F. Monteiro, A. Dandache, A. M'Sir and B. Lepley, 'A Fast CRC Implementation on FPGA Using a Pipelined Architecture for the Polynomial Division,' IEEE International Conference on Electronics, Circuits and Systems, Vol. 3, pp. 1231-1234, Sept. 2001 https://doi.org/10.1109/ICECS.2001.957437
  6. M.D. Shieh et al., 'A Systematic Approach for Parallel CRC Computations,' J. Information Science and Engineering, May 2001
  7. M. Spachmann, 'Automatic Generation of Parallel CRC Circuits,' IEEE Design and Test of Computers, Vol. 18, pp, 108-114, May 2001 https://doi.org/10.1109/54.922807
  8. G. Campobello, G. Patane and M. Russo, 'Parallel CRC Realization,' IEEE Transactions on Computers, Vol. 52, pp. 63-71, Oct. 2003 https://doi.org/10.1109/TC.2003.1234528
  9. Cypress Semiconductor Corporation, 'Parallel Cyclic Redundancy Check (CRC) for $HOTLINK^TM$,' Application note, Mar. 1999
  10. G.D. Micheli, Synthesis and Optimization of Digital Circuits. McGRAW-HIlL INTERNATIONAL EDITIONS, 1994