• 발명특허
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• v.10 no.5 s.111
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• pp.71-71
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• 1985

반도체, 컴퓨터, 통신기기 분야에서 최첨단 기술제품의 생산 공급을 통해 그동안 국내 전자산업을 선도해 온 금성반도체(대표 : 구자두)는, 지난해 6월 세계 3번째로 반주문형 초대규모 집적회로(VLSI)인 CMOS게이트 어레이를 개발하여 미국 엘에스아이 로직(LISLOGIC)사와 1억 5천만불의 수출계약을 체결함으로써 국내 최초로 주문형 반도체의 수출시대를 연데이어, 4월 10일 여의도 중심부 신한 빌딩 4층에 100여평 규모의 게이트 어레이 디자인 센터를 개관하여 특수한 반도체를 주문하는 고객이 동 제품의 회로 설계과정에 직접참여할 수 있도록 함으로써 수주활동을 본격화 하는 일대 전기를 마련하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of IKEEE
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• v.15 no.1
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• pp.23-28
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• 2011

This paper describes design and implementation of a spread spectrum clock generator(SSCG). The proposed architecture generates the spread spectrum clock controlling a input voltage signal for VCDL(Voltage Controlled Delay Line). Spread charge pump is controlled by the SSC modulation logic block provides a control signal to VCDL through LPF in DLL. By using this architecture, chip area and power consumption can be reduced because it is not necessary additional circuit to control modulation rate. This circuit has been designed and fabricated using the UMC 0.25um CMOS technology. The chip occupies an area of 290${\times}$120um^2.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.832-836
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• 2015

In this paper, a DC-DC converter is designed for logic process MTP (multi-time programmable) memory IPs using dual program voltage, which are used for analog trimming or storing chip IDs in sensor applications. The DC-DC converter supplies VPP (=5.25V), VNN (=-5.25V), and VNNL ($=2{\cdot}VNN/5$). It uses MOS capacitors and designed with only 3,3V devices. VPP and VNN are configured in two and five stages, respectively. And their pumping currents are $9.17{\mu}A$ and $9.7{\mu}A$, respectively.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.83-90
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• 2004

This paper describes on-board decentralized data acquisition system that acquires and encodes the numerous sensor data distributed on the big flight vehicles efficiently. The system's sub-units which have one encoder unit and several remote units were designed and simulated according to the communication protocols and the control, sequence logics based on the FPGA chip. And we have made the functional verification of the acquisition, collection and formatting of remote analog and digital data for the manufactured hardwares.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.2
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• pp.101-105
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• 2006

The Engineering Model of STSAT-2 on-board computer(OBC) was developed and tested completely with other sub-systems. The on-board computer of STSAT-2 has a high- performance PowerPC processors and a structure of centralized network communication. In addition, a lot of logics are implemented by Field Programmable Gate Array, such as interrupt controller, watchdog timer and UART. It could make the weight and size of OBC lighter and smaller. Also, the STSAT-2 on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-1.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.24-26
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• 2015

최근 많이 활용되고 있는 라즈베리파이에 기반한 임베디드 시스템을 구축함에 있어서 사용자는 회로에 대한 이해와 하드웨어 비용이라는 측면에서 어려움을 갖게 되는 경우가 많다. 본 논문에서는 이러한 시스템을 가상으로 테스트할 수 있는 솔루션을 제안하고자 한다. 개발된 프로그램은 사용자가 실제 회로를 구성하는 것과 같이 가상의 공간에서 모듈을 배치하고 모듈 간에 선을 연결하는 것으로 회로를 구성하고 동작을 테스트할 수 있다 프로그램은 회로편집기, 인터프리터, 시뮬레이터의 세 가지 요소로 구성되어 있으며 전체 9개의 모듈을 제공하고 있다. 각각의 모듈은 제조사에서 제공하는 데이터 시트와 제원을 바탕으로 실제 회로 테스트를 거쳐 추상화하는 작업을 수행하였다. 개발된 프로그램의 품질수준을 한층 끌어올린다면 비용절감과 학습, 교육 측면에서 유용하게 이용될 수 있으며, 전기물리엔진의 구현, 실제 보드로 포팅이 가능한 수준의 인터프리터, 시뮬레이션 로직의 일반화가 필요할 것으로 판단된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.