• Journal of Navigation and Port Research
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• v.26 no.3
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• pp.289-294
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• 2002

The broadband high power 3-way combiner was designed and fabricated for the digital TV repeater. To achieve increase of the bandwidth and the high power capability, Wilkinson type power divider was adopted in our research. First of all, Wilkinson type power divider of equal-split and unequal-split were combined, and the characteristics of the four port in-phase power combiner was simulated for each thickness of dielectric substrates. As the results of simulation, the power combiner fabricated by using dielectric substrate of 120 mil-thickness has the characteristics as follows: insertion loss of less than -651 dB, reflection coefficient of less than -13 dB, isolation among the output ports of less than -15 dB, and pose difference among the output ports of smiler than 13$^{\circ}$. Therefore, this power combiner was possible to improve the limit of microstrip line width due to high impedance, the problem of power loss due to interaction between strip lines in a high power combiner and narrow bandwidth simultaneously. Furthermore, making broadband and high power could be achieved since the fabricated 3-way combiner has good characteristics of insertion loss, the reflection coefficient, separation between ports, and phase difference.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.334-348
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• 2005

The goal of next generation digital broadcasting is offering the interaction among consumers and providers as well as variety services. One of the important factors for this new broadcasting environment keeps the interoperability among providers and consumers since the environment is distributed. Therefore a standard metadata for digital broadcasting is required and TV-Anytime metadata is one of the metadata standards for digital broadcasting. The terminal nodes of TV-Anytime metadata are defined by using MPEG-7 metadata. MPEG-7 metadata is standard metadata for describing multimedia content. Therefore, if we use the MPEG-7 metadata for describing broadcasting content can offer multimedia search services like content-based search by the extension of metadata. The efficient management system for these metadata is important for offering the services with high Duality on real broadcasting environment TV-Anytime metadata and MPEG-7 metadata are technically defined using a single XML schema, so its instances are XML data. Currently, a lot of systemsfor managing XML data are proposed in many researchers and we can expect to adapt these systems for managing broadcasting metadata. But the methods used in these systems are not specific methods for managing broadcasting metadata because of methods for general-purpose. In this paper, we find the properties of broadcasting metadata and develop an efficient metadata management system that is based on the found properties. Since our systemis implemented on real broadcasting environment, we expect that the system is most efficient and suitable. Also our system is interoperable since we use XQuery as query language for querying broadcasting metadata.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.52-59
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• 2007

In this paper, we analyzed and measured implant isolation characteristics for a 1.25 Gbps monolithic integrated hi-directional (M-BiDi) optoelectronic system-on-a-chip, which is a key component to constitute gigabit passive optical networks (PONs) for a fiber-to-the-home (FTTH). Also, we derived an equivalent circuit of the implant structure under various DC bias conditions. The 1.25 Gbps M-BiDi transmit-receive SoC consists of a laser diode with a monitor photodiode as a transmitter and a digital photodiode as a digital data receiver on the same InP wafer According to IEEE 802.3ah and ITU-T G.983.3 standards, a receiver sensitivity of the digital receiver has to satisfy under -24 dBm @ BER=10-12. Therefore, the electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysed and measured results of the implant structure, the M-BiDi SoC with the implant area of 20 mm width and more than 200 mm distance between the laser diode and monitor photodiode, and between the monitor photodiode and digital photodiode, satisfies the electrical crosstalk level. These implant characteristics can be used for the design and fabrication of an optoelectronic SoC design, and expended to a mixed-mode SoC field.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.215-224
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• 2003

This paper presents an electronic ballast using a novel complex modulation method for the metal halide lamp. The proposed modulation method, which has a modulating signal of swept complex frequency, can eliminate the acoustic resonance more effectively than the conventional modulation method, which has a modulating signal of constant frequency. For the purpose of future application specific integrated circuits (ASIC). the controller of the proposed ballast has been designed only with erasable programmable logic devices (EPLDs), but without a microprocessor. In this paper, detailed proposed modulation schemes are described and experimental results on the proto type 150W metal halide lamp ballast with the proposed modulation method ate discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.110-118
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• 2013

This paper describes the development of DSSS wireless communication uplink system for missile remote control. In consideration of low probability of intercept, low probability of exploitation, anti-jam, low latency, and doppler frequency offset, we used DSSS partially DBPSK. Also we used the selective diversity with two receiving antennas to mitigate multipath interference which is the dominant channel impairment and the turbo product code(TPC) for forward error correction(FEC) to improve bit error rate performance.

• Journal of IKEEE
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• v.15 no.2
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• pp.122-128
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• 2011

Although conventional analog linescan cameras are used widely, high-speed, high-resolution Cameralink standard will lead the area of frame grabber industry such as factory automation. In this paper, we are developing embedded frame grabber testbed without PC which will give an another solution to image processing applications. Therefore, we designed hardware schematics and programmed FPGA device with VHDL in order to interface Cameralink standard linescan CCD camera. In the future, our embedded on-chip controller could be applied to various image processing systems such as medical imaging, especially optical coherence tomography, machine vision and industrial electronics.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1219-1226
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• 2013

This study is the analysis and verification process of the L-band satellite communications repeater thought PCB & circuit EM analysis. System performance can be vulnerable to various spurious inside the L-band satellite transponder, power conversion board, digital signal board, TM/TC board, such as control panels and blocks that are linked signal components when the winch is increased due to the noise component. So the whole system can cause performance degradation. PCB resonance analysis and EM simulation can be easily analyzed for a variety of optimal. Also, by setting the ports on the PCB, H/W designer wants to can easily analyze system.