• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.271-272
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• 2014

현재 디지털 시스템 설계가 필요한 모든 유한 상태머신을 설계에는 필수적 밀리 모델이나 무어 모델이 들어간다. 그러나 각각의 기기와 기능에 따라서 밀리 모델과 무어 모델 중 어느 모델이 디지털 논리회로 설계에 효율적인지 판단이 모호한 상황이다. 이를 위해 본 논문에서는 유한 상태머신의 하나인 벤딩머신을 대상으로 밀리 모델과 무어 모델을 사용하여 설계한 후, 설계의 복잡도와 구현 게이트 수를 구하여 각 모델의 효율성에 대해 비교 분석하고자 한다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.5
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• pp.401-406
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• 2005

Digital memory circuits have been developed very fast according to the progress of semiconductor technology. But it was very difficult to memorize a wideband radio frequency signals. Many years ago, an analog frequency memory loop(FML) was used for store of radio frequency signal and the digital radio frequency memory was made according to the development of wideband amplifier and high speed sampler. We present a design of wideband digital radio frequency reproduction device using ladder circuit and the simulation results with respect to the sampling speed in this paper.

• Proceedings of the Optical Society of Korea Conference
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• 2001.08a
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• pp.204-205
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• 2001

• Journal of KIISE:Software and Applications
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• v.32 no.1
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• pp.62-73
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• 2005

Evolvable Hardware is the technique that obtains target function by adapting reconfigurable digital' devices to environment in real time using evolutionary computation. It opens the possibility of automatic design of hardware circuits but still has the limitation to produce complex circuits. In this paper, we have analyzed the fitness landscape of evolvable hardware and proposed a speciation technique of evolving diverse individuals simultaneously, proving the efficiency empirically. Also, we show that useful extra functions can be obtained by analyzing diverse circuits from the speciation technique.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.3
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• pp.94-100
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• 1999

In this paper, we are implemented the courseware targets to the integrated a digital system analysis, a design theory, and a hardware description language training and a logic analysis. This paper consists of two subjects. One is that the learning of a digital system analysis, that of a design theory, and the training of a hardware description language is simultaneously performed. The other is that the experiment of courseware. To learn the hardware description language, the explanation using sound or moving images, setting-up of a simulation or a synthesis program, and simulating are executed on a courseware. And also, we proposed an integrated systems for the hardware description language and a logic synthesis. Also, The reliablity of the tool was verified to be preyed an efficient operation of an implemented digital system courseware tool by korea computer research association.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.1
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• pp.31-38
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• 2024

The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10c
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• pp.306-308
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• 1998

본 논문에서는 멀티미디어 스트림을 제어하는 표준으로 Microsoft사에서 제안한 DirectShow의 특성을 살펴보고, 디지털 오디오 효과 필터 5가지에 대한 요소를 분석하며, 분석한 자료를 토대로 파라미터 및 기본 기능을 설계한다. 이러한 설계를 바탕으로 DirectShow를 이용하여 디지털 오디오 효과 필터를 구현한다. DirectShow는 윈도 95와 윈도 NT 기반의 멀티미디어 스트림 제어를 COM으로 구현할 수 있게 한다. 따라서 구현되는 필터의 삽입, 삭제, 변경, 등이 용이하게 된다. 이 논문에서 구현한 오디오 효과 필터 5가지는 오디오의 기본적인 특성을 이용하는 필터로서 오디오 필터 구현을 위한 핵심 기술이 많이 이용된 필터라고 할 수 있다.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.118-119
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• 2007

TWO-CHANNEL방식의 디지털 광센서는 I2C의 출력을 가지고 있다. 하나의 CMOS집적회로에 포토다이오드와 기존의 아날로그-디지털 변환기(ADC)로 구성되어 있었던 방식과는 달리 2개의 비교기(Comparotor)로 2개의 채널을 형성하게 된다. 인간의 눈과 비슷한 반응을 얻기 위해 16-bit의 유효 범위를 갖는다. 이 광센서는 광원의 넓은 파장에 적합하게 설계 되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.43-49
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• 2000

We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.6
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• pp.52-65
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• 1978

Computer-aided design of color TV circuits has been tried using circuit analysis programs. Due to the complexity of colorplexed composite video signals of the color TV, conventional methods are difficult to apply in the color TV circuit design. This paper describes how to design Y video circuit, chroma cicruit, AGC circuit, and sync separator circuit of color TV using analysis programs.