• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.207-209
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• 2018

본 논문은 고효율 및 고전력밀도 3-레벨 PFC(Power Factor Correction) 컨버터를 제안한다. 기존 PFC의 고 전력밀도를 위한 스위칭 주파수 상승은 스위칭 특성이 우수한 소자를 적용하거나, 별도의 스너버 회로가 요구되므로 설계가 복잡하며 고전력밀도 달성에 한계가 있다. 제안 PFC 컨버터는 3-레벨 방식을 적용하여 각 스위칭 소자의 전압 스트레스를 절반으로 감소시켰으며, 스위치 손실 저감을 통한 고속 스위칭 동작으로 리액티브 소자의 고밀도화를 달성하였다. 또한, 기존의 3-레벨방식은 디지털 제어를 통해 스위칭 소자의 전압 평형이 이루어졌지만, 본 논문에서는 아날로그 IC에 전압 평형을 위한 RC Delay 회로와 소수의 SMD(Surface-mount devices) 소자만을 이용하여 별도의 제어회로 없이 전압 평형이 가능하므로 고 전력밀도 달성에 유리하다. 제안회로의 타당성을 검증하기 위해 CRM(Critical conduction mode) PFC 컨버터를 기반으로 250W급 시작품 제작을 통한 실험 결과를 제시한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.2
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• pp.255-265
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• 1999

Recently the necessity of MMIC is increasing because clock frequency goes up by digital data transmission of Gbps class being demanded and the density of circuits gets high for the purpose of lightening and miniaturizing system, owing to the development of ultra high speed. When massing lines in a MMIC and super high speed integrated circuit cause the crosstalk and dispersion of signal, a digital signal is distorted and EMI is occurred. To solve this problems, It is necessary to analyze the equivalent parameters of transmission lines. This paper represent the results of the equivalent parameters of transmission lines for single and hi-level structure by using moment method.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.11-18
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• 2011

This study developed a digital security device which power is on/off by the RFID card. This device is based on the wireless data transmit/receive circuits, built in RS-232C chip and applied to computer and other digital devices. We can check whether this device is operated or not by connecting the LED. In this system, 13.56MHz frequency circuit supplies power with ID card, and DC inputs check the proximity operating distance of the card field for verifying the existence of a card. The security level of this system is much stronger than that of a compared system[13]. Anyone cannot use the system without RFID card. All illegal access is prevented except for authorized path.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.8
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• pp.784-789
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• 2011

In this paper, a tunable integrated transmitter leakage canceller based on an autotransformer for ultra-high-frequency (UHF) RFID readers is presented. The proposed TX leakage canceller consists of an autotransformer, a digital tuning capacitor, a voltage controlled tuning resistor, and a compensating amplifier, and it is designed using 0.13 ${\mu}m$ 1-poly 6-metal RF CMOS process. The simulation results show that the proposed structure has over 55 dB rejection characteristic between a transmitter and a receiver and a 2.5 dB of the RX insertion loss. The TX leakage canceller can be digitally tuned from 825 MHz to 985 MHz with the tuning capacitor and it can be fully integrated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.989-998
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• 2012

A ratio type of capacitance measurement circuit is proposed to measure an extremely small value of the fF capacitance on this paper. This measurement circuit is formed with a switched-capacitor integrator, a comparator, and logic circuit blocks to control the switches. It converts the measured ratio value between the known value of on-chip capacitor and the unknown value of capacitor to the digital signal. The fF capacitance with minimized error can be obtained by calculating this ratio. This proposed circuit is designed with standard CMOS $0.18{\mu}m$ process, and various HSpice simulations prove that this capacitance measurement circuit is able to measure the capacitance under 5fF with less than ${\pm}0.3%$ error rate.

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.2
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• pp.7-16
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• 2019

Neural networks can be implemented in variety of ways, and specialized chips is being developed for hardware improvement. In order to apply such neural networks to wearable devices, the compactness and the low power operation are essential. In this point of view, a suitable implementation method is a digital circuit design using field programmable gate array (FPGA). To implement this system, the learning algorithm which takes up a large part in neural networks must be implemented within FPGA for better performance. In this paper, a back propagation algorithm among various learning algorithms is implemented using FPGA, and this neural network is verified by OR gate operation. In addition, it is confirmed that this neural network can be used to analyze various users' bio signal measurement results by learning algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.13-22
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• 2001

This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9％ reduction in volume and 4.8cm, 28.4％ in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.97-102
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• 2007

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is implementation of a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• 한국정보교육학회:학술대회논문집
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• 2010.08a
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• pp.19-25
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• 2010

Education delivers knowledge through story. On that point Storytelling is related to education. However, the problem is raised that Storytelling in school is leaning toward teachers that's why it makes students passive story listeners. Therefore, this study developed Digital Storytelling material using in the education for elementary school students. It leads them to be able to interact actively. So, I organized applicable 12 themes for 24 times training contents in after-school tutoring program because Digital Storytelling education doesn't perform in elementary school yet. If the material is used in classes, I expect to increase learners' self-expressiveness and creativity, and besides to train the ability of adapting and taking the lead in this changing society by contributing the spread of the Digital Storytelling education. Finally, in a follow-up study, it is demanded to verify an educational effect of this material and to redesign the process of these material contents through application in studying.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.145-151
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• 2004

For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.