• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.469-471
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• 2019

본 논문은 신호에 포함되어 있는 다양한 잡음을 효과적으로 제거할 수 있는 프로그램 가능한 디지털 유한 임펄스 응답 필터를 제안한다. 이러한 필터는 복잡도 등을 고려하여 3차 회로로 설계되어 있다. Altera사의 FPGA(Field Programmable Gate Array)인 cyclone II EP2C70F89618를 이용하여 설계하였다. 신호에 포함된 미세하고 다양한 잡음을 제거하기 위한 알고리즘을 개발하였다. 이를 바탕으로 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 다양한 잡음에 대해 우수한 출력 영상을 확인하였다.

• The Journal of the Convergence on Culture Technology
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• v.6 no.2
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• pp.515-520
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• 2020

CMOS used in digital circuit design technology has reached the limit of integration due to quantum tunneling. Quantum-dot cellular automata (QCA), which can replace this, has many advantages such as low power consumption and fast switching speed, so many digital circuits of CMOS have been proposed based on QCA. Among them, the multiplexer is a basic circuit used in various circuits such as D-flip-flops and resistors, and has been studied a lot. However, the existing multiplexer has a disadvantage that space efficiency is not good. Therefore, in this paper, we propose a new multilayered multiplexer using cell interaction and D-latch using it. The multiplexer and D-latch proposed in this paper have improved area, cell count, and delay time, and have excellent connectivity and scalability when designing large circuits. All proposed structures are simulated using QCADesigner to verify operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.983-990
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• 2003

In this paper, a noncoherent code tracking loop is designed for 3GPP MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. An analytical closed-form formula for steady-state jitter variance is Int derived for AWGN environments as a general function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth, together with the analysis on the transient response characteristic of a tracking loop. Based on the analysis, the code tracking loop with variable loop bandwidth that is efficient for full digital H/W implementation is designed and its performance is compared with that of the code tracking loop with fixed loop bandwidth, along with the verification by computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.83-90
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• 2004

This paper describes on-board decentralized data acquisition system that acquires and encodes the numerous sensor data distributed on the big flight vehicles efficiently. The system's sub-units which have one encoder unit and several remote units were designed and simulated according to the communication protocols and the control, sequence logics based on the FPGA chip. And we have made the functional verification of the acquisition, collection and formatting of remote analog and digital data for the manufactured hardwares.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2141-2152
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• 1998

In this paper, we design and implement an indoor wireless modem using small signal of ISM band regulation, which can tranceive reliable data streams. We use direct sequence spead spectrum (DS-SS) signaling with synchronous BPSK and QPSK modulation, convolutional coding with viterbi decoding. The radio frequency module uses frequency devision duplexing in 900 MHz band, and the digital module is implemented with FPGAs for the purpose fo ASIC design. The perfomrance of our own acquistion and tracking circuit consisting digital matched filter and decision logic is proved by experiments, and the possibility of file transfer at indoor environment with the entrie system that the modem is connected the PC through RS-232C port is verified.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.350-353
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• 2015

최근 에너지 효율과 소형화측면에서 한계를 보이는 Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET)을 대체할 수 있는 소자로 Tunneling FET(TFET)이 주목받고 있다. 본 논문에서는 탄소나노튜브(Carbon Nanotube, CNT) TFET을 시뮬레이션하여 전자회로의 기본 단위인 인버터(Inverter)를 설계한다. 설계한 인버터의 성능을 CNT-MOSFET 인버터와 비교하여 저전력 디지털 회로로써의 가능성을 확인한다.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.43-45
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• 2008

컨버터의 제어는 보통 아날로그 제어기를 기반으로 한다. 전용 아날로그 상용 IC들로 복잡한 회로의 장점을 극복하고 있고 이로 인해 기본성능을 수행하고 저가격화와 사용상의 편의를 얻을 수 있다. 그러나 이러한 장점은 디지털 제어기의 성능 개선과 가격의 하락으로 전용의 IC에 필적하는 파워 컨버터의 응용을 가능하게 만들었다. DC-DC 컨버터 내부 파라미터에 대한 모니터링이 가능하며, 아날로그 제어방식에서는 처음의 사양에 의해 고정된 출력전압을 얻었지만 디지털 제어 방식에서는 PC와 DC-DC 컨버터간 통신을 통하여 사용자가 원하는 임의의 전압을 얻어낼 수 있고 원격제어가 가능하다. 본 논문에서는 이와 같은 디지털 제어기의 장점과 실용성을 제시하고자 소신호 모델식을 기반으로 하여 디지털 모드 제어기를 설계하고, 이를 구현하기 위해 원칩 마이크로컨트롤러인 microchip사의 dsPIC30F2020을 사용하였다. 마이크로컨트롤러를 이용한 DC-DC 컨버터의 실용성을 검토하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.68-73
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• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• Korean Journal of Optics and Photonics
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• v.11 no.4
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• pp.239-245
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• 2000

In this paper, the fundamental properties of diffractive optical element were investigated. Also, this work deals with theoretical approaches for achromatization in DOE's optical system based on thin lens theory. It is found that achromatization could be satisfied by one hybrid lens only, which is composed of a diffractive and a refractive element. In order to have compact optical system, we used the tele-photo type lens composed of a positive and a negative power elements instead of retro-focus lens. From the Gaussian brackets and Seidel aberration theory, the initial design was numerically obtained. The aberration properties of an initial design was aplanat and flat field. In order to correct the chromatic aberrations, refractive and diffractive elements were used on front element. This hybrid lens is also useful for correction of higher order aberrations. Compared to conventional design composed of refractive lenses only, this approach dramatically improved the compactness of the optical system. Finally, residual aberration balancing results in a lens with focal length of 3.89 mm and overall length of 5.19 mm, which has enough performance over an f-number of 4.0. Also, it is expected to fulfill all the requirements of a digital still camera lens. This optical system is superior to the current refractive lens system in the number of elements, weight, and aberration properties. rties.