• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.30-39
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• 2017

A digital calibration technique based on digital-domain averaging for cyclic ADC is proposed. The proposed calibration compensates for nonlinearity of ADC due to capacitance mismatch of capacitors in 1.5-bit/stage MDAC. A 1.5-bit/stage MDAC with non-matched capacitors has symmetric residue plots with respect to the ideal residue plot. This intrinsic characteristic of residue plot of MDAC is reflected as symmetric A/D transfer functions. A corrected A/D transfer function can be acquired by averaging two transfer functions with non-linearity, which are symmetric with respect to the ideal analog-digital transfer function. In order to implement the aforementioned averaging operation of analog-digital transfer functions, a 12-bit cyclic ADC of this work defines two operational modes of 1.5-bit/stage MDAC. By operating MDAC as the first operational mode, the cyclic ADC acquires 12.5-bits output code with nonlinearity. For the same sampled input analog voltage, the cyclic ADC acquires another 12.5-bits output code with nonlinearity by operating MDAC as the second operational mode. Since analog-digital transfer functions from each of operational mode of 1.5-bits/stage MDAC are symmetric with respect to the ideal analog-digital transfer function, a corrected 12-bits output code can be acquired by averaging two non-ideal 12.5-bits codes. The proposed digital calibration and 12-bit cyclic ADC are implemented by using a $0.18-{\mu}m$ CMOS process in the form of full custom. The measured SNDR(ENOB) and SFDR are 65.3dB (10.6bits) and 71.7dB, respectively. INL and DNL are measured to be -0.30/-0.33LSB and -0.63/+0.56LSB, respectively.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.9
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• pp.877-882
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• 2011

In this paper, thermal deformation of a double ring structure using digital image correlation technique (DIC) was measured. The double ring structure consisted of two parts; the inner ring was aluminium which had a large thermal expansion coefficient and the outer ring was titanium which had a small thermal expansion coefficient. We heated the double ring structure from $50^{\circ}C$ to $200^{\circ}C$ in a chamber and at the same time, two cameras captured surface images of the double ring structure. Initially, there was a 21 ${\mu}m$ gap between the inner ring and outer ring. The gap was closed at around $80^{\circ}C$ and after that, two rings expanded together. In order to compare the experimental results with analysis results, a finite element analysis was performed using ANSYS. The results of DIC measurement and ANSYS analysis were compared and agreed well.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.675-678
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• 2007

그래픽스 분야에서 다양한 재질을 사실감 있게 표현하려는 연구가 활발히 진행되고 있는 가운데, 다양한 재질의 반사특성을 측정하는 방법들이 시도되고 있고 이때 광디텍터로 디지털카메라를 이용하면서 HDR 영상으로부터 광량을 추정한다. 그러나, 디지털카메라는 분광광도계와 달리 컬러보정이 필요하며 이로부터 생성된 HDR 영상 역시 컬러가 보정되어야 한다. 본 연구에서는 일반적으로 HDR 영상을 생성하기 전에 LDR 영상들의 컬러를 보정하는 방법의 문제점을 제시하고, 직접적으로 HDR 영상의 컬러를 보정하는 HDR-레벨 컬러보정 방법을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.3
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• pp.11-16
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• 2000

In this paper, a real-time implementation of scene-based non-uniformity correction by digital technique is proposed for microscan-mode staring infrared cameras. Most scene-based non-uniformity correction algorithms, without sensor motion, can not be applied to stationary scenes because of image blurring and fading. Using microscanning effect, coupled with a modified version of Scribner's algorithm, the proposed technique can correct the artifacts and non-uniformities in real time Computer simulations and hardware experiments demonstrate substantial Improvement of image qualities in stationary as well as moving scenes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Journal of Digital Convergence
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• v.17 no.2
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• pp.217-230
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• 2019

This study was conducted to develop a customized severity-adjustment method and to evaluate their validity for acute myocardial infarction(AMI) patients to complement the limitations of the existing severity-adjustment method for comorbidities. For this purpose, the subjects of KCD-7 code I20.0 ~ I20.9, which is the main diagnosis of acute myocardial infarction were extracted using the Korean National Hospital Discharge In-depth Injury survey data from 2006 to 2015. Three tools were used for severity-adjustment method of comorbidities : CCI (charlson comorbidity index), ECI (Elixhauser comorbidity index) and the newly proposed CCS (Clinical Classification Software). The results showed that CCS was the best tool for the severity correction, and that support vector machine model was the most predictable. Therefore, we propose the use of the customized method of severity correction and machine learning techniques from this study for the future research on severity adjustment such as assessment of results of medical service.

• Journal of Digital Convergence
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• v.11 no.5
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• pp.371-384
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• 2013

The purpose of this study was to develop the risk-adjusted mortality model using Korean Hospital Discharge Injury data and US National Hospital Discharge Survey data and to suggest some ways to manage hospital mortality rates through comparison of Korea and United States Hospital Standardized Mortality Ratios(HSMR). This study used data mining techniques, decision tree and logistic regression, for developing Korea and United States risk-adjustment model of in-hospital mortality. By comparing Hospital Standardized Mortality Ratio(HSMR) with standardized variables, analysis shows the concrete differences between the two countries. While Korean Hospital Standardized Mortality Ratio(HSMR) is increasing every year(101.0 in 2006, 101.3 in 2007, 103.3 in 2008), HSMR appeared to be reduced in the United States(102.3 in 2006, 100.7 in 2007, 95.9 in 2008). Korean Hospital Standardized Mortality Ratios(HSMR) by hospital beds were higher than that of the United States. A two-aspect approach to management of hospital mortality rates is suggested; national and hospital levels. The government is to release Hospital Standardized Mortality Ratio(HSMR) of large hospitals and to offer consulting on effective hospital mortality management to small and medium hospitals.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.436-439
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• 2011

본 논문은 클록 보정회로를 가진 1V 2.56-GS/s 6-bit flash analog-to-digital converter (ADC) 제안한다. 제안하는 ADC 구조에서 아날로그 블록은 단일 T/H와 2단의 프리앰프, 그리고 비교기를 사용된다. 2단의 프리앰프와 비교기의 출력에 옵셋의 크기를 줄이기 위하여 저항 평균화 기법을 적용하였다. 디지털 블록은 quasi-gray rom base 구조를 사용한다. 3입력 voting 회로로 flash ADC에서 발생하기 쉬운 bubble error를 제거하였으며, 고속 동작을 위해 단일 클록을 사용하는 TSPC F/F로 구현한다. 제안하는 flash ADC는 클록 듀티 비를 조절할 수 있는 클록 보정회로를 사용한다. 클록 보정 회로는 비교기 클록 듀티 비를 조절하여 리셋 시간과 evaluation 시간의 비율을 최적화함으로 dynamic 특성을 확보한다. 제안한 flash ADC는 1V 90nm의 CMOS 공정에서 설계되었다. Full power bandwidth인 1.2 GHz 입력에 대하여 ADC 성능을 시뮬레이션을 통해 확인하였다. 설계된 flash ADC의 면적과 전력소모는 각각 $800{\times}400\;{\mu}m^2$와 193.02mW 이다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.1-6
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• 2010

The lens distortion in the machine vision system is inevitable phenomenon. Distortion is getting worse, due to the selection of lens in the trend of reducing prices and size of the system. In this trend, the distortion correction becomes more important. But, the traditional correction methods has problems, such as complexity and requiring more operations. Effective distorted digital image correction is the precondition of target detection and recognition based on vision inspection. To overcome the disadvantage of traditional distortion correction algorithms, such as complex modeling, massive computation and marginal information loss, an image distortion correction algorithm based on photogrammetry method is proposed in this paper. In our method, we use the lattice image as the measurement target. Through the experimental results, we could find that we can reduce the processing time by 4ms. And also the inspection failure rate of our method was reduced by 2.3% than human-eyes inspection method.

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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• 2000.10a
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• pp.40-50
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• 2000

본 연구에서는 Rolleiflex 6006 측정용 카메라로 촬영된 사진과 DCS 420 디지털 카메라로부터 촬영된 화상을 이용, 수치근접사진측량을 실시한 후, 조경석의 표면 거칠기 측정 정확도 향상을 위하여 최소제곱법으로 기준평면 또는 기준곡면을 찾아 사용하는 방법을 연구하였으며, 조경석 표면의 연마 이전과 연마 이후의 표면 거칠기를 측정, 비교하여 연마후의 거칠기 감소크기를 산출하고, 측정 정확도를 알아보기 위하여 거칠기가 거의 없는 평면인 돌과 곡면인 돌의 표면 거칠기를 측정한 결과, 그 거칠기를 기대정확도 이상인 각각 $\pm$0.lmm 및 $\pm$0.2mm의 정확도로 측정할 수 있었다. 또한 측정용 카메라인 경우 렌즈왜곡 보정에 있어서 검정자료를 토대로 기준점을 사용하지 않는 직접보정방법인 Newton-Raphson법을 적용하여 기하학적 정확도가 향상된 수치사진화상을 얻을 수 있었으며, DCS 420 디지털 카메라와 윈도우 운영체계인 Visual basic 6.0을 이용하여, 표면 거칠기 측정시스템을 구축함으로써 연마이전 조경석과 연마이후 조경석에 대한 표면 거칠기 및 형상을 정밀 측정할 수 있는 수치근접사진측량기법을 제시할 수 있었다.