• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.95-103
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• 2007

Dynamic voltage scaling (DVS) is a well-known and effective power management technique. While there has been research on slack distribution, voltage allocation and other aspects of DVS, its effects on non-voltage-scalable devices has hardly been considered. A DC-DC converter plays an important role in voltage generation and regulation in most embedded systems, and is an essential component in DVS-enabled systems that scale supply voltage dynamically. We introduce a power consumption model of DC-DC converters and analyze the energy consumption of the system including the DC-DC converter. We propose an energy-optimal off-line DVS scheduling algorithm for systems with DC-DC converters, and show experimentally that our algorithm outperforms existing DVS algorithms in terms of energy consumption.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1051-1055
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• 2010

Software defined radio(SDR) technology implements wireless communication protocols as software instead of dedicated hardware. SDR enables reconfiguration of wireless communication protocols without expensive hardware modification. However, as the SDR systems are equipped with additional programmable processors, they suffer significant power dissipation. This paper proposes a novel power management technique for SDR systems, called the combined modulation and voltage scaling (CMVS). Numerical analyses were performed to evaluate the effectiveness of CMVS. The results show that CMVS minimizes power dissipation while satisfying the given data transfer rate.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.641-650
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• 2008

As portable devices are used widely, power management algorithm is essential to extend battery use time on small-sized battery power. Although many methods have been proposed, they assumed the voltage transition overhead was negligible or was considered partially. However, the voltage transition overhead might not guarantee to schedule real-time tasks in portable multimedia systems. This paper proposes the adaptive power-aware algorithm to minimize the power consumption by considering the voltage transition overhead. It selects only a few discrete frequencies from the whole frequencies of a system and adjusts the interval between two consecutive frequencies based on the system utilization to reduce the number of frequency change. This algorithm saves the power consumption about 10 to 25 percent compared to a CC RT-DVS method and a frequency-smoothing method.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.10
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• pp.543-552
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• 2004

This paper proposes an energy optimization technique for latency and quality constrained video applications. It consists of two key techniques: frame-skipping technique and buffering technique. While buffering increases the slack time utilization at the OS level. frame skipping Increases the slack time itself at the application level, and both enhance the effectiveness of the dynamic voltage scaling technique. We use an H.263 encoder application as a test vehicle to which the proposed technique is applied. Experiments demonstrate that the proposed technique achieves noticeable energy reduction satisfying the given latency and video quality constraints.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.10
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• pp.562-574
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• 2004

We address the problem of energy-optimal voltage scheduling for fixed-priority hard real-time systems. First, we prove that the problem is NP-hard. Then, we present a fully polynomial time approximation scheme (FPTAS) for the problem. for any $\varepsilon$>0, the proposed approximation scheme computes a voltage schedule whose energy consumption is at most (1+$\varepsilon$) times that of the optimal voltage schedule. Furthermore, the running time of the proposed approximation scheme is bounded by a polynomial function of the number of input jobs and 1/$\varepsilon$. Experimental results show that the approximation scheme finds more efficient voltage schedules faster than the best existing heuristic.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.1-6
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• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.443-443
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• 2010

액체 표면을 전극으로 하는 플라즈마 방전은 생물학적 살균, 분해 처리 등에 필요한 UV 및 화학적 활성종의 생성에 유리하여 널리 활용되고 있다. 하지만 그 특성 등에 관한 연구는 액체막의 유동 및 기하학적 구조 상 진단의 제한으로 인하여 아직 미비한 상태이다. 전해질 내 방전은 전극 표면의 기포 막 에 인가되고 그 두께에 따라 변한다. 따라서 본 연구에서는 액상 전해질의 인가 전압 및 점성도를 독립적으로 조절하여 기포 막 크기와 인가 전력간의 관계와 이에 따른 전해질 내 플라즈마의 특성이 음극 글로우 방전임을 밝혔다. 실험에서는 전기 전도도 1.6-3.2 S/m의 NaCl 수용액 전해질에 양극성 전극을 삽입하고 350 kHz의 전압을 인가하여 플라즈마를 발생하였다. 인가된 전압은 230 - 280 V이며 전해질의 점성도는 젤라틴을 첨가하여 1E-4-1.1 kg/m${\times}$sec로 조절하였다. 기포 막의 두께 및 변화는 고속카메라를 통하여 관측하였으며 인가되는 전압 및 전류는 고전압 프로브와 전류 프로브를 통하여 관찰하였다. 기포 막은 전극표면에서 막 비등을 통하여 발생됨을 밝혔다. 인가 전력과 손실 열에너지간의 비율에 따라 기포막은 수축과 확장의 진동을 반복하였으며 전기 유체적 모델을 통하여 기포 막의 동적 거동에 따른 플라즈마에 인가된 전력의 변화를 정량적으로 분석할 수 있었다. 기포 막의 평균적인 두께는 인가 전압과 비례하여 약 $150\;{\mu}m$에서 $200\;{\mu}m$로 증가하였으며 진폭은 점성의 증가 시 약 $50\;{\mu}m$에서 $20\;{\mu}m$로 감소하였다. 순간적인 플라즈마 인가 전력은 평균적인 두께에 따른 평균적인 두께에 대해서는 15 - 20 W의 변화를 보였으나 진폭의 감소 시 17 - 70 W의 보다 큰 폭으로 증가하였다. 이를 통하여 점성도가 큰 조건에서 기포 막의 확장이 억제되어 방전이 유지됨을 알 수 있었다.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.309-310
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• 2008

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.151-153
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• 2003

이 논문은 프레임 기반의 비디오 응용에 대해서 화질 (video quality) 제약을 고려한 응용 수준(application-level)에서의 에너지 최적화 기법을 제안한다. 화질과 에너지 소모 사이에는 상관관계 (trade-off)가 있음을 이용하여. 본 논문은 H.263 인코더의 화질을 실시간으로 모니터링해서 프레임 속도(frame rate)를 자동으로 조절하는 알고리즘을 제안한다. 기존 동적 전압 스케줄링 (DVS: dynamic voltage scheduling) 기법은 유휴 시간 (slack time)을 주어진 것이라고 가정하는 반면, 제안하는 기법은 유휴 시간 자체를 증가시켜서 DVS 기법의 효과를 향상시킨다. 제안하는 기법이 주어진 화질 제약을 만족하며 상당한 에너지 소모를 감소함을 실험을 통해서 알 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.