• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of IKEEE
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• v.25 no.3
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• pp.473-478
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• 2021

Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.

• Journal of IKEEE
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• v.22 no.4
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• pp.1168-1174
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• 2018

For the initial state of NAND flash memories, error-free and single-error cases are dominant due to a good channel environment on memory cells. It is important to deal with such cases, which affects the overall system performance. However, the conventional schemes for polar codes equally decode the codes even for the error-free and single-error cases since they cannot classify and decode separately. In this paper, a new pre-processing scheme for polar codes is proposed so as to improve the overall decoding latency by decoding the frequent error-free and single-error cases. Before the ordinary decoding process, the proposed scheme first decodes the frequent error-free and single-error cases. According to the experimental results, the proposed pre-processing scheme decreases the average decoding latency by 64% compared to the conventional scheme for (1024, 512) polar codes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.685-690
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• 2021

In this paper, we propose a deep learning-based transmit power control scheme to maximize the sum-rates while satisfying the minimum data-rate in downlink non-orthogonal multiple access (NOMA) systems. In downlink NOMA, we consider the co-channel interference that occurs from a base station other than the cell where the user is located, and the user feeds back the signal-to-interference plus noise power ratio (SINR) information instead of channel state information to reduce system feedback overhead. Therefore, the base station controls transmit power using only SINR information. The use of implicit SINR information has the advantage of decreasing the information dimension, but has disadvantage of reducing the data-rate. In this paper, we resolve this problem with deep learning-based training methods and show that the performance of training can be improved if the dimension of deep learning inputs is effectively reduced. Through simulation, we verify that the proposed deep learning-based power control scheme improves the sum-rate while satisfying the minimum data-rate.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.139-149
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• 2003

In this paper a hardware design of area-efficient hash processor which implements MD5 algorithm using hardware sharing and carry-save addition schemes is described. To reduce area, the processor adopts hardware sharing scheme in which 1 step operation is divided into 2 substeps and then each substep is executed using the same hardware. Also to increase clock frequency, three serial additions of substep operation are transformed into two carry-save additions and one carry propagation addition. The MD5 hash processor is designed using 0.25 $\mu\textrm{m}$CMOS technology and consists of about 13,000 gates. From timing simulation results, the designed MD5 hash processor has 465 Mbps hash rates for 512-bit input message data under 120 MHz operating frequency.

• Journal of Internet Computing and Services
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• v.23 no.5
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• pp.25-31
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• 2022

In ultra dense networks (UDNs), macro user equipments (MUEs) have significant interference from small-cell access points (SAPs) since a number of SAPs are deployed in the coverage of macro base stations of 5G mobile communication systems. In this paper, we propose a dynamic channel assignment scheme to increase the performance of MUEs for the uplink of UDNs even though the number of SAPs is increased. The target of the proposed dynamic channel assignment scheme is that the signal-to-interference and noise ratio (SINR) of MUEs is above a given SINR threshold assigning different subchannels to SUEs from those of MUEs. Simulation results show that the proposed dynamic channel assignment scheme outperforms others in terms of the mean MUE capacity even though the mean SUE capacity is decreased a little lower.

• Clean Technology
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• v.15 no.3
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• pp.202-209
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• 2009

N-incorporated $WO_3$ ($WO_3$:N) films were synthesized using a reactive RF magnetron sputtering on unheated substrate and then post-annealed at different temperatures from 300 to $500^{\circ}C$ in air. The N anion narrowed optical band gap, due to its mixing effect with the O 2p valence states. Furthermore, it was found that the crystallinity of the $WO_3$:N films was significantly improved by the post-annealing at $350^{\circ}C$ and higher. As a result, the $WO_3$:N films exhibited much better photoelectrochemical performance, compared with pure $WO_3$ films post-annealed at the same temperature.

• Journal of the Korean Geotechnical Society
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• v.25 no.4
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• pp.31-38
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• 2009

A continuous, fast, and convenient experimental method, replacing recent tests such as standard oedometer or self weight consolidation test, is needed for the determination of the consolidation behavior of unformed soft soils. This study introduced the seepage induced fast consolidation test using the flow pump technique. It can obtain the consolidation characteristics of unformed soft soils conveniently and fast. The seepage induced consolidation test apparatus consists of a modified triaxial cell, differential pressure transducer, flow pump, and displacement transducer. The test continuously proceeds with starting seepage forces induced consolidation, loading consolidation, and permeability test on the same sample. In addition, this test result was compared with the standard oedometer test result to make this method valid. From this study it was found that this method is a convenient and time saving effective method for obtaining data required for calculation of consolidation settlement of unformed soft soils.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.227-236
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• 2017

Quantum-dot cellular automata(QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Various circuits on QCA have been researched until these days, a latch required for counter and state control has been proposed as a component of sequential logic circuits. A latch uses a feedback loop to maintain previous state. In QCA, a latch uses a square structure using 4 clocks for feedback loop. Previous latches have been proposed using many cells and clocks in coplanar. In this paper, in order to eliminate these defects, we propose a SR and D latch using multilayer structure on QCA. Proposed three dimensional loop structure is based on multilayer and consists of 3 layers. Each layer has 2 clock differences between layers in order to reduce interference. The proposed latches are analyzed and compared to previous designs.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.73-77
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• 2023

In this study, we developed a Multi-level FeRAM (Ferroelectrics random access memory) device utilizing different ferroelectric materials and analyzed its operation through C-V analysis using simulations. To achieve Multi-level operation, we proposed an MFM (Multi-Ferroelectric Material) structure by depositing two different ferroelectric materials with distinct properties horizontally on the same bottom electrode and subsequently adding a gate electrode on top. By analyzing C-V peaks based on the polarization phenomenon occurring under different voltage conditions for the two materials, we confirmed the feasibility of achieving Multi-level operation, where either one or both of the materials can be polarized. Furthermore, we validated the process for implementing the proposed structure using semiconductor fabrication through process simulations. These results signify the significance of the new structure as it allows storing multiple states in a single memory cell, thereby greatly enhancing memory integration.