• Proceedings of KOSOMES biannual meeting
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• 2005.11a
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• pp.197-202
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• 2005

Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection using subpixel edge detection method in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.793-799
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• 2007

Generally, a semiconductor chip measured with a few micro units is captured by line scan camera for higher inspection accuracy. However, the faulty inspection requires an exact boundary detection algorithm, because it is very sensitive to scan speed and lighting conditions. In this paper we propose boundary detection with subpixel edge detection in order to increase the accuracy of bump faulty detection on chips. The bump edge is detected by first derivative to four directions from bump center point and the exact edge positions are searched by the subpixel method. Also, the exact bump boundary to calculate the actual bump size is computed by LSM(Least Squares Method) to minimize errors since the bump size is varied such as bump protrusion, bump bridge, and bump discoloration. Experimental results exhibit that the proposed algorithm shows large improvement comparable to the other conventional boundary detection algorithms.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.17-21
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• 2008

The electroless plating of copper and tin were investigated for the fabrication of Sn-Cu bump. Copper and tin were electroless plated in series on $20{\mu}m$ diameter copper via to form approximately $10{\mu}m$ height bump. In electroless copper plating, acid cleaning and stabilizer addition promoted the selectivity of bath on the copper via. In electroless tin plating, the coating thickness of tin was less uniform relative to that of electroless copper, however the size of Sn-Cu bump were uniform after reflow process.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.663-674
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• 2003

Bump mapping is a technique that represents the detailed parts of the object surface, such as a perturberance of the skin of a peanut, using the geometry mapping without complex modeling. However, the hardware implementation for bump mapping is considerable, because a large amount of per pixel computation, including the normal vector shading, is required. In this paper, we propose a new bump mapping algorithm using the polar coordinate system and its hardware architecture. Compared with other existing architectures, our approach performs bump mapping effectively by using a new vector rotation method for transformation into the reference space and minimizing illumination calculation. Consequently, our proposed architecture reduces a large amount of computation and hardware requirements.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.37-41
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• 2014

One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.77-84
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• 2006

Surface roughness and wafer-level thickness distribution of the non-cyanide Au bumps were characterized with variations of the electroplating current density and the bath temperature. The Au bumps, electroplated at $3mA/cm^{2}\;and\;5mA/cm^{2}$, exhibited the surface roughness of $80{\sim}100nm$ without depending on the bath temperature of $40^{\circ}C\;and\;60^{\circ}C$. The Au bumps, electroplated with $8mA/cm^{2}$ at $40^{\circ}C\;and60^{\circ}C$, exhibited the surface roughness of 800nm and $80{\sim}100nm$, respectively. Wafer-level thickness deviation of the Au bumps became larger with increasing the current density from $3mA/cm^{2}\;to\;8mA/cm^{2}$. More uniform thickness distribution of the Au bumps was obtained at a bath temperature of $60^{\circ}C$ than that of $40^{\circ}C$.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.20 no.4
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• pp.381-389
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• 2010

Modern military equipments are often required to be mounted on a truck for their survivability and operation performance. Special units installed on the truck at times experience serious shock vibration caused by obstacles of road and/or uncommon road shape. It is then essential to analyze the travel performance of truck-mounted special units for their survivability and performance. In this paper, shock responses of the equipments subjected to bump passing and wash board road are experimentally obtained and also analyzed via FEM. Modified bump configuration and road profile considering the interface with tire are suggested. Analytical results considering this modification show good agreement with test results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.641-642
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• 2009

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.