• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6B
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• pp.544-552
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• 2003

This paper suggests an instruction code sufficiency algorithm preventing data collision when multiple transponders attempt to connect in the radio frequency identification system. Conventional time domain procedure generates unconditional collision. On the other hand, this algorithm prevents data collision by transmitting data when it meets instruction code. When multiple transponders are transmitting data coincidently, they exploit desired data with using difference of arrival time generated by recognition distance, respectively. As a result of simulation, utilizing the wireless recognition system, adopting the suggested algorithm, operating in 13.56MHz frequency band, it verify that there is Anti-collision and data loss by ensuring transmission time difference of one bit by adopting this algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.4
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• pp.519-529
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• 1993

A spectral and power efficient modulation technique, named Compact Superposed Quadrature Amplitude Modulation (Compact-SQAM), is introduced. The performance of Compact-SQAM system, in a Linearly and nonlinearly amplified single and multicarrier environment, in the presence of additive white Gaussian noise(AWGN), intersymbol interference(ISI), timing jitter and adjacent channel interference (ACI), is experimentally analyzed via computer simulation. Various channel conditions, such as channel spacing, between the main and adjacent channels and fade depth on the desired main channel, are examined. Our result shows that Compact-SQAM, and better P(e) performance that other modems using simple Butteroworth type postdetection receive filters. Especially, Compact-SQAM modem achieves higher efficiency of frequency utilization and better P(e) performance than other modems in the severly bandlimited nonlinear multicarrier channels.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.1
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• pp.54-61
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• 2009

This paper proposes the 2nd-order SDSDM (Space Dithered Sigma-Delta Modulation) for performance improvement of a buck converter. The PWM (Pulse Width Modulation) has a drawback in that power spectrum tends to be concentrated around the switching frequency. The resulting harmonic spikes cause a EMI(Electromagnetic Interference) and switching loss in semiconductor, etc. The 1st-order SDSDM scheme is a kind of DSDM for reducing these harmonic spikes. In this scheme, a switching frequency is spread through random dither generator placed on input part. In experimental result, the proposed 2nd-order SDSDM is confirmed by applying to a buck converter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• Korean Journal of Optics and Photonics
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• v.16 no.5
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• pp.411-416
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• 2005

We have designed an extended L-band Erbium-doped fiber amplifier to amplify 1625 nm optical time domain reflectometry signal for a long distance monitoring system. The proposed amplifier has a dual-stage structure without an isolator. Gain improvement of 5.1 dB has been achieved by adding a fiber Bragg grating and a narrow band pass filter. As a result, the 16.3 dB gain and 7.1 dB noise figure has been successfully accomplished.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.11
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• pp.48-53
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• 2007

In this paper, a high LO-RF isolation W-band MIMIC single-balanced mixer was designed and fabricated using a branch line coupler and a ${\lambda}/4$ transmission line. The W-band MIMIC single-balanced mixer was designed using the $0.1\;{\mu}m$ InGaAs/InAlAs/GaAs Metamorphic HEMT diode. The fabricated MHEMT was obtained the cut-off frequency($f_T$) of 154 GHz and the maximum oscillation frequency($f_{max}$) of 454 GHz. The designed MIMIC single-balanced mixer was fabricated using $0.1\;{\mu}m$ MHEMT MIMIC process. From the measurement, the conversion loss of the single-balanced mixer was 12.8 dB at an LO power of 8.6 dBm. P1 dB(1 dB compression point) of input and output were 5 dBm and -8.9 dBm, respectively. The LO-RF isolations of single-balanced mixer was obtained 37.2 dB at 94 GHz. We obtained in this study a higher LO-RF isolation compared to some other balanced mixers in millimeter-wave frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.3 s.106
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• pp.249-258
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• 2006

In this letter, we propose a novel printed helix antenna for RFID reader in UHF band. The printed strip line of the antenna is first wound up outside a polygonal shaped layer and then the winding continues on an inner layer to control the overall gain and the radiation pattern. In addition, the winding pitch angles on each layer have either negative or positive values resulting in the broad CP bandwidth. The detail structure of the antenna was optimized using Pareto genetic algorithm(GA), so as to obtain excellent performances for RFID reader antennas. The optimized two-layered polygonal helix was fabricated on the cardboard of a flexible substrate and the performances were measured and compared with the simulations. The fabricated antenna was made up of copper tape which can adhere to a flexible cardboard and had 21.4 % matching bandwidth, 31.9 % CP bandwidth, readable range of $5.5m^2$ with kr=3.2. Also based on the current distribution of the strip line of the antenna and sensitivity of the antenna bents points, we confirmed that the antenna has the quarter-wave transformer near the feed for the broad matching bandwidth and radiates the traveling wave for the broad CP bandwidth using the bent strip line.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.18-24
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• 2007

We report broadband cascode amplifiers of a single-ended and a balanced amplifier for the millimeter-wave applications. The amplifiers were fabricated using 0.1 ${\mu}m\;{\Gamma}-gate$ PHEMT technology on GaAs substrate. The single-ended cascode amplifier was designed and fabricated by using shunt peaking technology. The fabricated single-ended cascode amplifier shows 3 dB bandwidth of 37 GHz($18.5{\sim}55.5$ GHz) and the maximum $S_{21}$ gain of 9.38 dB. The balanced cascode amplifier using tandem couplers achieves 3 dB bandwidth and the maximum $S_{21}$ gain of 44.5 GHz($21{\sim}65.5$ GHz) and 10.4 dB at 60 GHz, respectively. The 3 dB bandwidth of the balanced cascode amplifier shows 20% lager than the single-ended cascode amplifier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.