• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.419-425
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• 2017

This paper presents CMOS UWB RFIC based radar system for high speed target detection. The system can achieve resolution of 15 cm and detection range of 15 m. For developed system, single chip CMOS UWB IC is implemented. To reduce the measuring and processing time, envelope detection and equivalent time sampling technique are used. Measurement results show that the bandwidth and center frequency of UWB pulse can be adjusted in the range of 0.5 GHz~1.0 GHz, 3.5 GHz~4.5 GHz, respectively. Signal processing time including scan time over 15 m distance is about $150{\mu}sec$.

• The Journal of the Acoustical Society of Korea
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• v.20 no.3
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• pp.83-90
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• 2001

Conventional SAW duplexer filters employ a 1/4 wavelength transmission line, which causes difficulty in fabrication of the strip line on the package. Its manufacturing process is also complicated, because it needs integrating process of the separate transmitting filter, receiving filter and isolation circuits. This paper concerns development of a new structure of the duplexer filter that has all the transmitting filter, the receiving filter and the isolation circuit as a one chip device. For composition of the duplexer, we design the component SAW ladder filters and the isolation network consisting of lumped inductor and capacitor elements. Performance of the whole duplexer is optimized by the nonlinear multivariable minimization of a proper target function, and the result is compared with that of commercial filters.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

This paper presents a new low-cost fault-based Built-In Self-Test (BIST) scheme and technique for 1.8GHz RF receiver front end. The technique utilizes input impedance matching measurement. The BIST block and RF receiver front end are designed using 0.25m CMOS technology on a single chip. The technique is simple and inexpensive. The overhead of the BIST circuit is approximately $10\%$ of the total area of the RF front end.

• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.443-447
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• 2005

EMAST(Embedded Mobile Automatic System for Telematics) is implemented in SoC using the CAN and ARM Processor. For the general usage, EMAST must satisfy the two condition. First, Mobile internal interface is to be designed to support Differential Transceiver, Optical Transceiver and Wireless Transceiver Second, it should be supporting the interface between terminals using EMAST and telematics networks. In this paper, we propose EMAST structure and the efficient interface structure between EMAST and each mobile units.

• Korean Journal of Materials Research
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• v.11 no.5
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• pp.385-392
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• 2001

There have been many investigations and researches on PLC type of optical amplifiers because they are convenient for mass production and also can integrate multi-functional devices into a single chip. In this research. the fabrication of optical waveguide made of Si/$Sio_2$ by FHD(Flame Hydrolysis Deposition) for passive integrated optical devices and $1.5\mu\textrm{m}$ optical amplifier by Solution Doping method, which is one of the method doping $Er^{3+}$ into the thin film, are mainly discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.9
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• pp.951-962
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• 1992

The layout of electrical power distribution networks never involved communications aspects. As a result their transmission properties severly complicate the use as data links. Futhermore bandwidth as well as transmission power is restricted. Nevertheless, power distribution net works represent a most attractive medium for digital communication purposes due to an ever increasing demand, e.g., for environment management of buildings, office automation, and remote meter reading or security monitoring. In this paper, a power line modem which is capable of transmitting and receiving data at 1200 bps using OOK-BASK through 220V AC power lines is implemented. The receiver includes noncoherent detector and performs soft decision. The OLM circuits can be simplified by use of microprocessor. The PLM also satisfies CENELEC, European standards, and can be applied to home automation system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1595-1599
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• 2001

In this paper, we have desired and implemented of ASK modulator MMIC operating at 5.8 GHz for OBE used in AGPS(Automatic Gate Passing System). The proposed ASK modulator MMIC was implemented to apply a single supply voltage of 3 V to the drain in order to decrease ACP(Adjacent Channel Power). As a result, it is exhibits a broad linear modulation range from 0.7 V to 3 V and an On/off characteristic over 40 dB. The layouts of ASK modulator MMICs was designed and fabricated by using ETRI 0.57m MESFET library The chip size was 1.0mm $\times$x1.0mm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.886-889
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• 2006

수치연산 보조프로세서로도 알려져 있는 부동 소수점 연산장치(FPU)는 컴퓨터가 사용하는 기본 마이크로프로세서보다 더 빠르게 숫자를 다를 수 있는 특별한 회로 설계 또는 마이크로프로세서를 말한다. FPU는 전적으로 대형 수학적 연산에만 초점을 맞춘 특별한 명령 셋을 가지고 있어서 그렇게 빠르게 계산을 수행할 수 있는 것이다. FPU는 오늘날의 거의 모든 PC에 장착되고 있지만, 실은 그것은 그래픽 이미지 처리나 표현 등과 같은 특별할 일을 수행할 때에 필요하다. 초창기 컴퓨터 회사들은 각기 다른 연산방식을 사용했다. 이에 따라 연산결과가 컴퓨터마다 다른 문제점을 해결하기 위해 IEEE에서는 부동 소수점에 대한 표준안을 제안하였다. 이 표준안은 IEEE Standard 754 이며, 오늘날 인텔 CPU 기반의 PC, 매킨토시 및 대부분의 유닉스 플랫폼에서 컴퓨터 상의 실수를 표현하기 위해 사용하는 가장 일반적인 표현 방식으로 발전하였다. 본 논문에서는 부동 소수점 표준안 중 32-bit 단일 정밀도 부동 소수점 가산기를 VHDL로 구현하여 FPGA칩으로 다운하고 PCI 인터페이스를 통해 Visual C++로 데이터의 입출력을 검증하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.