• Journal of the Korean Data and Information Science Society
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• v.26 no.5
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• pp.1035-1045
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• 2015

Recent studies in Big Data Analysis are showing promising results, utilizing the main memory for rapid data processing. In-memory computing technology can be highly advantageous when used with high-performing servers having tens of gigabytes of RAM with multi-core processors. The constraint in network in these infrastructure can be lessen by combining in-memory technology with distributed parallel processing. This paper discusses the research in the aforementioned concept applying to a test taxi hailing application without disregard to its underlying RDBMS structure. The application of IMDG technology in the application's backend API without restructuring the database schema yields 6 to 9 times increase in performance in data processing and throughput. Specifically, the change in throughput is very small even with increase in data load processing.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.244-253
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• 2000

Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.477-485
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• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.

• The Magazine of the IEIE
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• v.19 no.4
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• pp.1-7
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• 1992

IBM이 16비트 PC를 처음 선보인 81년 이후 오늘에 이르기까지 10여년간의 운영체제(0S) 시장은 마이크로소프트(MS)사의 독주시대로 요약할 수 있다. 그러나 지금까지 이렇다 할 변화를 보이지 않던 OS제품은 90년대에 들어서면서 커다란 변화의 조짐에 횝싸이고 있다. 그동안 8086, 80286등의 마이크로프로세서를 탑재한 16비트 PC시장이 80386,80486등을 탑재한 32비트 시장으로 급변하기 시작했고 종전 데스크탑 일변도의 PC시장은 랩톱,노트북형 등의 휴대형컴퓨터와 펜컴퓨터,멀티미디어 등의 차세대 제품등으로 세분화되기 시작한 것이다. 또 32비트 시대가 다가오면서 한사람이 한 대의 PC로 일을 하는 종전 PC운용환경은 넷워킹과 멀티테스킹이 강조되는 다중작업 환경으로 전환되고 있으며 윈도즈(Windows) 3.0의 대히트로 IBM PC에서도 GUI(그래픽 사용자인터페이스) 환경을 요구, 이를 위한 새로운 05의 등장이 불가피해지고 있다. 게다가 지금까지 메인프레임을 중심으로 한 중앙집중방식의 컴퓨터환경이 다운사이징화 되면서 넷워크 환경을 기반으로 한 PC의 역할이 크게 강조, 이를 위한 운영체제 또한 새로운 영역으로 대두되고 있다. 불과 1∼2년 사이에 급진전되고 있는 이같은 변화의 물결은 필연적으로 다양한 운영체제의 개발을 가져왔고 이를 통해 차세대 PC시장을 주도하기 위한 업계의 패권다툼은 전쟁을 방불케할 만큼 치열해지고 있다. MS사의 전유물이었던 DOS 영역에서는 최근 노벨사와의 합병으로 전열을 가 다듬은 디지틀리서치사가 가세, 한판승부를 선언하고 나섰으며 고성능 PC시대의 패권을 잡기 위해 10년지기였던 IBM과 MS사는 각각 OS/2와 윈도즈를 내세우고 양보할 수 없는 힘겨루기에 들어갔다. 또 이들 양사는 펜컴퓨터,멀티미디어등 차세대제품의 운영체제 시장을 둘러싸고 일찍부터 격전에 들어갔으며 IBM과 MS사의 혼전을 틈타 썬마이크로시스템을 필두로한 워크스테이션 업체 및 유닉스진영까지 고성능 PC시장을 겨냥한 OS를 속속 개발, 90년대의 OS 전쟁은 한치 앞을 내다볼 수 없는 안개국면으로 접어들고 있다. DOS에서 32비트시대,펜컴퓨터, 멀티미디어에 이르는 차세대제품을 둘러싼 업계의 OS 쟁탈전을 통해 OS의 발전동향과 미래를 전망해 본다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2409-2417
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• 1994

The ODR(orthogonal double-rotation) digital lattice filters have desirable properties for VLSI implementation such as local connection, regularity and pipelinability. These filters are also known to exhibit good numerical behavior for finite precision implementation. Although these filters can be pipelined by the cut-set localization procedure, it should be noted that the maximum sample rate obtained by this technique is limited by the feedback computations. In this paper, a pipelining method for the ODR digital lattice filter is proposed, by which the sample rate can be increased at any desired level. it is also shown that the low-power CMOS digital implementation of ODR digital lattice filters can be done successfully using our pipelining method. The pipelining method is based on the properties of the Schur algoithm, constrained filter design methods, and the polyphase decomposition technique.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• The KIPS Transactions:PartB
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• v.12B no.2 s.98
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• pp.191-202
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• 2005

The Semantic Web Services is a next-generation Web technology that supports Web services, based on the semantic Web technologies. Until now, the researches on semantic Web services may be foiled on the semantic Web document management and the inference engine to efficiently process the semantic Queries. However, in order to realize the principle semantic Web environment it is necessary to provide a semantic query interface though which users and/or agents can efficiently request semantic information. In this regard, we propose the Semantic Query Adapter(SQA) to provide a high query transparency with users, especially when querying about a complex semantic information. We first design the procedural user query interface based on a graphic view, by analyzing DAML-S Profile documents. And then, we builds a module which a user input query transforms its corresponding RDQL. We also propose the multiple semantic query generating procedure as a new method to solve the disjunctive query problem of the RDQL primitive.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.643-657
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• 2004

The chordal ring based CC-NUMA system contains many links to transmit transactions between a local node and a remote node because of its structural characteristics. However, the inclination that the transactions concentrate on the ring link increases both the traffic of the ring link and the response time, which degrades the overall performance of the chordal ring based CC-NUMA system. In this paper we suggest a new remote cache replacement policy that considers both the number of total links and the number of ring links to traverse for the transactions. Our proposed replacement policy can balance data between the ring link and the chordal link properly because it reflects the characteristics of chordal ring based CC-NUMA system well.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2914-2922
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• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.