• Korean Journal of Construction Engineering and Management
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• v.16 no.6
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• pp.53-62
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• 2015

Time-Cost Trade-Off (TCTO) model is an important model in the construction project planning and control area. Two types of Existing TCTO model, continuous and discrete TCTO model, have been developed by researchers. However, Using only one type of model has a limitation to represent a realistic crash scenario of activities in the project. Thus, this paper presents a comprehensive TCTO model that combines a continuous and discrete model. Additional advanced features for non-linear relationship, incentive, and liquidated damage are included in the TCTO model. These features make the proposed model more applicable to the construction project. One CPM network with 6 activities is used to explain the proposed model. The model found an optimal schedule for the example to satisfy all the constraints. The results show that new model can represent more flexible crash scenario in TCTO model.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.978-980
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• 2006

A Next Generation Network (NGN) is a packet-based network able to provide services including Telecommunication Services and able to make use of multiple broadband, QoS-enabled transport technologies and in which service-related functions are independent from underlying transport-related technologies. It offers unrestricted access by users to different service providers. It supports generalized mobility which will allow consistent and ubiquitous provision of services to users In this paper, we explain the trend of standardization activity related with open services in ITU-T SG13(Study Group 13). ITU-T SG13 is responsible for studies .elating to the architecture, evolution and convergence of next generation networks including frameworks and functional architectures, signalling requirements for NGN.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of the Korea Society for Simulation
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• v.25 no.3
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• pp.85-95
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• 2016

In National Defense field, the importance of M&S and T&E has been increased due to complexity of modern Weapon System. And research reducing time and cost is being conducted continually on using limited resources efficiently. In the existing research, Weapon System's Performance Evaluation System using the Process-based method has been in progress. But, Objective basis or scientific method is insufficient in selecting appropriate function of a target to performance evaluation. Due to this, it's difficult to select functions suitable to the situation in same type. Also, Requirements of user and interrelation of evaluation factors can't be reflected systematically. In this research, it proposes the method to reflecting requirements of user, interrelation of elements in realistic situation for selecting evaluation object in Performance Evaluation Simulation. First, Evaluation Objects is selected using ANP which is multi-criterion decision making method. Second, decision support system is constructed using Programming Language(C#) based on the research result.

• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1451-1461
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• 2019

DNS spoofing is an attack in which an attacker intervenes in the communication between client and DNS server to deceive DNS server by responding to a fake IP address rather than actual IP address. It is possible to implement a pharming site that hacks user ID and password by duplicating web server's index page and simple web programming. In this paper we have studied web spoofing attack that combines DNS spoofing and pharming site implementation which leads to farming site. We have studied DNS spoofing attack method, procedure and farming site implementation method for portal server of this university. In the case of Kyungsung Portal, bypassing attack and hacking were possible even though the web server was SSL encrypted and secure authentication. Many web servers do not have security measures, and even web servers secured by SSL can be disabled. So it is necessary that these serious risks are to be informed and countermeasures are to be researched.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.291-298
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• 2022

A generative adversarial network (GAN) is a network in which two internal neural networks (generative network and discriminant network) learn while competing with each other. The generator creates an image close to reality, and the delimiter is programmed to better discriminate the image of the constructor. This technology is being used in various ways to create, transform, and restore the entire image X into another image Y. This paper describes a method that can be forged into another object naturally, after extracting only a partial image from the original image. First, a new image is created through the previously trained DCGAN model, after extracting only a partial image from the original image. The original image goes through a process of naturally combining with, after re-styling it to match the texture and size of the original image using the overall style transfer technique. Through this study, the user can naturally add/transform the desired object image to a specific part of the original image, so it can be used as another field of application for creating fake images.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.585-587
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• 2022

The visual motivation between AP devices is NTP-based visual motivation through the access of the Internet through the internal wired LAN, but this has several seconds of visual difference in hundreds of milliseconds (msec) depending on the network. The frame for the output of the video will vary depending on the application, but usually 24 (image) frames are output to the screen in one second. Therefore, the visual synchronization between peripheral devices can be performed through the adjacent moving camera device, not the wired method. The programming method of generating API for synchronization command when creating an application for visual synchronization and delivering it to AP through MAC may differ from the time in synchronization command according to the environment of the operating system at the transmission side and the situation of the buffer queue of the MAC. Therefore, as a method to solve this problem, the renewal of visual information in the device driver terminal controlling MAC can be much more effective.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.23 no.2
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• pp.1-14
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• 2024

The most optimal route-search algorithm thus far has introduced a method of applying node labels and link labels. Node labels consider two nodes simultaneously in the optimal route-search process, while link labels consider two links simultaneously. This study proposes a turn-label-based optimal route-search technique that considers two turns simultaneously in the process. Turn-label-based optimal route search guarantees the optimal solution of dynamic programming based on Bellman's principle as it considers a two-turn search process. Turn-label-based optimal route search can accommodate the advantages of applying link labels because the concept of approaching the limit of link labels is applied equally. Therefore, it is possible to reflect rational cyclic traffic where nodes allow multiple visits without expanding the network, while links do not allow visits. In particular, it reflects the additional cost structure that appears in two consecutive turns, making it possible to express the structure of the travel-cost function more flexibly. A case study was conducted on the metropolitan urban railway network consisting of transportation card terminal readers, aiming to examine the scalability of the research by introducing parameters that reflect psychological resistance in travel with continuous pedestrian transfers into turn label optimal path search. Simulation results showed that it is possible to avoid conservative transfers even if the travel time and distance increase as the psychological resistance value for continuous turns increases, confirming the need to reflect the cost structure of turn labels. Nevertheless, further research is needed to secure diversity in the travel-cost functions of road and public-transportation networks.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.1-11
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• 2020

In this paper, we present a technique that executes MPI parallel programs, that are developed on processor-centric computer architecture, more efficiently on memory-centric computer architecture without program modification. The technique we present here improves performance by replacing low-speed data communication over the network of MPI library functions with high-speed data communication using the property called fast large shared memory of memory-centric computer architecture. The technique we present in the paper is implemented in two programs. The first program is a modified MPI library called MC-MPI-LIB that runs MPI parallel programs more efficiently on memory-centric computer architecture preserving the semantics of MPI library functions. The second program is a simulation program called MC-MPI-SIM that simulates the performance of memory-centric computer architecture on processor-centric computer architecture. We developed and tested the programs on distributed systems environment deployed on Docker based virtualization. We analyzed the performance of several MPI parallel programs and showed that we achieved better performance on memory-centric computer architecture. Especially we could see very high performance on the MPI parallel programs with high communication overhead.