• Proceedings of the Korean Society of Computer Information Conference
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• 2021.07a
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• pp.317-320
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• 2021

본 연구는 주기적인 알츠하이머 병의 중증도 모니터링을 위해 스마트 인솔을 통한 보행 특징 추출과 머신러닝 기반 중증도 분류의 성능에 대해 살펴보았다. 최근 고령화가 가속화되는 추세에 있어 치매 환자가 급증하고 있으며, 중증도가 심해질수록 필요한 치료 비용 및 노력이 급증하기 때문에 조기 진단이 최선의 치료 전략으로 보여진다. 환자 친화적이고 저비용의 관성 측정 장치가 내장된 스마트 인솔만을 사용하여 다양한 보행 실험 패러다임에서 환자의 보행 특징을 추출하고, 이를 알츠하이머 병의 중증도 진단을 위한 머신러닝 기반 분류기를 훈련시켜 성능을 평가한 결과, 숫자세기와 같이 뇌에 부하를 주는 하위 작업이 포함된 복합 보행을 측정한 데이터셋을 사용하여 훈련된 분류 모델이 일반 걷기 데이터셋을 사용한 모델보다 성능이 높게 나타나는 것이 관찰되었다. 본 연구는 안전하고 환경적 제약이 적은 방법을 사용하여 시기 적절한 진단뿐만 아니라 주기적인 중증도 모니터링 시스템의 일환으로 활용될 수 있을 것이다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.1
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• pp.53-57
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• 2010

This study proposes the algorithm which drives the powerless without battery. The exiting wire or RF type dosimeter, which is the computation of the real time with battery on the dose radiation exposure, In the Wired dosimeter, it is trouble to need the maintenance and management by periods. Besides, the case of the RF typed dosimeter with battery, it is requested to size bigger and to replace battery frequently and so on. Especially RF typed dosimeter has trouble to need for the embody with large power consumption on the contactless typed dosimeter. As the method for the low power, the study designed to be down the operating clock of the MPC, to improve the efficiency of the rectifier, to eliminate the external memory and the DC-DC converter for the simplification of the circuit We convince our research contributes not only to understand the simplified circuit and miniaturization, but also to help the design and application technology of the powerless dosimeter.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.1-8
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• 2005

This paper proposes a new type of a dual-band internal antenna for GPS/PCS handsets. The antenna has three monopoles in different lengths, and this structure is referred as a 3-fingers type antenna in this paper. The antenna with low-profile structure is designed to use internal space of handset maximally. The fabrication and the measurement are accomplished by attaching the 3-finger type antenna to the inside of a commercial handset. We obtain gain of 1.97 dBi$\~$0.66 dBi in the GPS band, and -0.92 dBi$\~$1.02 dBi in the PCS band and almost omni-directional patterns at all bands.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.66-73
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• 2002

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.65-75
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• 2011

As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

• Korean Journal of Digital Imaging in Medicine
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• v.17 no.1
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• pp.19-31
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• 2015

최근 우리나라의 암 발생률은 꾸준히 증가추세에 있고 그 중에서도 전립선암은 갑상선암을 제외했을 때 남성에서 가장 높은 증가 추세를 보이고 있는 암이다. 전립선암은 그 동안 선진국에서 주로 발병하는 것으로 알려진 암 종이지만 서구화된 식습관과 생활 행태 변화로 인하여 국내에서도 발생률이 증가하는 것으로 추정하고 있다. 따라서 국내 환경에 맞는 내장 지방 분포와 같은 정확한 비만도 측정을 통해 우리나라에서 증가율 1위를 보이고 있는 전립선암 발생의 원인 관계를 찾고자 한다. 본 연구는 환자와 정상군 비교를 하는 환자-대조군 연구이고 본 연구를 위하여 임상시험 윤리위원회 (IRB) 승인을 받았다 (NCC2014-0124). 환자군은 2014년 8월 1일부터 2015년 1월 6일 까지 국립암센터를 방문하여 전립선암을 진단받고 수술과 항암치료 그리고 방사선 치료를 시작하지 않은 초진을 대상으로 하였고, 정상군은 2009년 11월부터 2014년 9월 30일까지 공단검진을 목적으로 국립암센터를 방문한 정상인을 대상으로 하였다. 전립선암 연구는 환자 총 52명에 평균 66세 (51 - 82세)이고 정상군은 총 50명에 평균 64세 (59 - 75세) 이다. 모든 연구 대상자들의 생활 요인 평가를 위하여 암 가족력, 흡연, 음주 상태, 운동, 등을 추가적으로 설문 조사하였다. MRI 영상의 배꼽 주위에서의 내장 지방과 피하지방을 전용 분석 컴퓨터를 활용하여 측정 하였다. 복부비만율은 환자군과 정상군에서뿐만 아니라 (p = 0.03), 전립선암 악성도와 (Gleasonscore; p = 0.001)도 통계적 차이를 나타냈다. 하지만 BMI 결과와는 전립선암 발생과 악성도에서 무관함을 보인 것에 반해 허리둘레는 전립선암의 발생에 영향을 미치는 결과를 나타났다. 한편 전립선암의 또 다른 악성도 지표인 PSA는 비만 측정치와의 상관성이 Gleason score와 보다 대체적으로 낮게 나타났다. 학력, 운동량, 흡연, 음주 상태와 같은 생활 특성에 따른 전립선암 발생의 영향 관계는 뚜렷하지 않았다. 결론적으로 본 연구를 통해서 전립선암의 발생 위험도와 악성도 지표로 복부 비만도가 유용함을 나타냈고 간단한 신체 계측 지표 활용으로는 BMI보다 허리둘레 측정치가 더 암 발생의 연관성이 높음을 보였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.855-862
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• 2003

This paper suggests the PIFA structure modified antenna in which short-circuit plate is located between planar element and ground plane, in order to solve the problem of narrow band of existing internal antenna, PIFA. It is also suggested that internal antenna has the perturbation in the patch to broaden the frequency bandwidth. It is possible that the antenna is installed into the mobile telephone with a low profile condition(h=0.015 λ) to use internally, and acquired desired bandwidth(5.2 %) through double resonance structure, remodeling the PIFA that is already well-known as an internal antenna. This paper investigated how characteristic is affected by the feeding point(Yf, Zf), short strip plate(Zs), short strip width(Ws), perturbation width(w), length(d), short plate height(h), dielectric($\varepsilon$$\_$r/) to be slim type antenna. It is compared with existing PIFA bandwidth, and is suggested pattern as the H.E plane. It is simulated using the Microwave Studio of the CST Inc. based on FIM(Finite Integration Method) method and analyzed antenna characteristic following the variation each parameters. The result proved the practical use of PIFA antenna by comparing the measured and simulated data of the antenna.

• Journal of the Institute of Convergence Signal Processing
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• v.20 no.3
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• pp.118-124
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• 2019

Recently, the industrial field has been changed to the smart factory system based on information and communication technology (ICT) in order to improve productivity, quality and customer satisfaction. The most important machine to realize the smart factory is the AGV(automatic guided vehicle) and the adoption of AGV is increasing. Generally, AGV is developed using general purpose PLC(Programmable Logic controller), but the price of AGV is expensive and its volume is large. On the other hand, the industrial field due to space constraints in the workplace is required the low cost AGV which can be minimization, expansion of function, and easily reconfiguration. Therefore, in order to solve these problems, this study is proposed a design method of AGV controller with built-in PLC, and evaluated its performance. In the results of the experimentation, it showed good performance (speed control error = 0.021[m/s], posture control error=2.1[mm]) for the speed and posture control. In this way, when applying the proposed AGV controller in this study to the industrial filed, it is possible to reduce the size and reconfigure at low cost.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.3
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• pp.111-116
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• 2013

With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES.