• Korean Architects
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• no.7 s.327
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• pp.98-103
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• 1996

국민체육진흥공단에서는 올림픽기념관 건립을 위한 설계경기를 실시, 지난 5월21일 희림건축(이영희)안을 당선작으로 선정,발표했다. 총 13개 사무소에서 참여한 이번 설계경기는 한국 스포츠의 과거, 현재, 미래를 상징하는 삼각형태의 건축구조를 이루고 있는 당선작외에 우수작은 예도건축(김동찬)안이, 가작으로는 김상경건축(김상경), 모양건축(박민수), 모람건축(김흥수)안이 각각 선정됐다. 이 기념관은 오는 99년 완공될 예정이다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2009.04a
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• pp.488-491
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• 2009

본 논문에서는 응력함수와 Kantorovich method를 이용하여 기저판(substrate)에 인장과 굽힘이 작용할 때 복합재 패치의 3차원 응력을 해석하였다. 면내 방향과 면외 방향의 두 응력함수에 가상 공액일의 법칙(Complementary virtual work principle)을 적용하였으며 복합재 패치의 자유 경계조건과 바닥의 기저판으로부터 전달되는 전단 수직 응력 조건을 부여하였다. 이를 통해서 패치 구조물의 지배방정식을 연립 미분 방정식 형태의 고유치 문제로 변환하여 응력함수를 구하였다. 위 방법의 타당성과 효용성을 검증하기 위한 수치 예제로 cross-ply, angle-ply, quasi-isotropic의 패치 적층 배열을 고려하였으며, 층간 응력함수 값이 자유 경계에서 최고치를 나타내고 패치 중심부로 갈수록 급격히 감소하는 모습을 확인하였다. 제안된 기법은 기저판에 인장하중이 작용하는 경우뿐만 아니라 굽힘 하중이 작용하는 경우에도 정확한 예측이 가능하여, 패치 구조물의 층간 응력을 포함한 3차원 응력을 해석하는데 있어서 효율적인 해석 도구로서 사용할 수 있을 것이라 사료된다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2617-2620
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• 2003

This paper presents the construction algorithm of the irreducible polynomial which needs to multiply over GF(2$\^$m/) and the flow chart representing the proposed algorithm has been proposed. And also, we get the degree from the value of xm＋k formation to the value of k = 7 using the proposed flow chart. The multiplier circuit has been implemented by using the proposed irreducible polynomial generation(IPG) algorithm in this paper, and we compared the proposed circuit with the conventional one. In the case of k = 7, one AND gate and five Ex-or gates are needed as the delay time for the irreducible polynomial in the proposed algorithm, but seven AND gates and sever Ex-or gates in the conventional one. As a result, the proposed algorithm shows the improved performance on the delay time.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.57-63
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• 1994

The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.3
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• pp.45-51
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• 1980

In this paper, a method for constructing Galois switching functions is presented. Single variable Galois switching function is constructed at fi tost by developing Lagrange's Interpolating formula into polynomial forms and then the constructing theory for two variables is driveloped. With these developed theory, multitle-variable Galois switching functions are constructed. Some examples for illustrating the theory are adopted from the existing papers and the results quite agree with the ones in the other papers.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.05a
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• pp.188-191
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• 2005

Taguchi method is used to determine the optimal configuration of PZT (Lead Zirconate-Titanate) patch on the host structure for improving the performance of piezoelectric shunt system. The charges generated on the surface of PZT patch are selected to be the objective function in the Taguchi method. Full three dimensional finite element models are used to simulate vibration of smart panel and to obtain the admittance of the piezoelectric shunt system. Using Taguchi method in Minitab, the optimal model is obtained. The experiment with piezoelectric shunt circuit is performed to verify the validity of the optimal model comparing with initial model.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.05a
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• pp.192-195
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• 2005

In this study, dynamic characteristics of an end-capped hull structure with surface bonded piezoelectric actuators are studied. Finite element modeling is used to obtain practical governing equation of motion and boundary conditions of smart hull structure. Modal analysis is conducted to investigate the dynamic characteristics of the hull structure. Piezoelectric actuators are attached where the maximum control performance can be obtained. Active controller based on Linear Quadratic Gaussian (LQG) theory is designed to suppress vibration of smart hull structure. It is observed that closed loop damping can be improved with suitable weighting factors in the developed LQG controller.