• Title/Summary/Keyword: 관통홀

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Evaluation on Effective Width of Concrete Unfilled Composite Steel Grid Deck (콘크리트 비충전 강합성 바닥판의 유효폭 평가)

  • Park, Young Hoon;Lee, Seung Yong
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.37 no.3
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    • pp.521-529
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    • 2017
  • In this study, analyzed the effective width of concrete unfilled composite steel grid deck which has different shear connector details from that of composite bridge. The effective width of concrete unfilled composite steel grid deck according to effective width calculation method, load size and main bearing bar spacing-span ratio was evaluated. As a result of analysis, it is analyzed that the effective width is calculated to be nearly equal to the actual effective width by idealizing the stress shape as a trapezoidal shape. In addition, shear hole penetration reinforcing bars applied to increase the shear strength is shown to increase the effective width. From the results of the analysis of the effective width according to main bearing bar spacing-span ratio, proposes the correction factor that can calculate the effective width ratio of the unfilled steel composite steel grid deck.

Interconnection Processes Using Cu Vias for MEMS Sensor Packages (Cu 비아를 이용한 MEMS 센서의 스택 패키지용 Interconnection 공정)

  • Park, S.H.;Oh, T.S.;Eum, Y.S.;Moon, J.T.
    • Journal of the Microelectronics and Packaging Society
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    • v.14 no.4
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    • pp.63-69
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    • 2007
  • We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

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Development of the Structure for Enhancing Capillary Force of the Thin Flat Heat Pipe Based on Extrusion Fabrication (압출형 박판 히트파이프의 모세관력 향상을 위한 구조 개발)

  • Moon, Seok Hwan;Park, Yoon Woo
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.40 no.11
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    • pp.755-759
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    • 2016
  • The use of heat pipes in the electronic telecommunication field is increasing. Among the various types of heat pipes, the thin flat heat pipe has relatively high applicability compared with the circular heat pipe in the electronic packaging application. The thin flat heat pipe based on extrusion fabrication has a simple capillary wick structure consisting of rectangular cross sectional grooves on the inner wall of the pipe. Although the groove serves as a simple capillary wick, and many such grooves are provided on the inner wall, it is difficult for the grooves to realize a sufficiently high capillary force. In the present study, a thin flat heat pipe with a wire bundle was developed to overcome the drawback of poor capillary force in the thin flat heat pipe with grooves, and was evaluated by conducting tests. In the performance test, the thin flat heat pipe with the wire bundle showed a lower thermal resistance of approximately 3.4 times, and a higher heat transfer rate of approximately 3.8 times with respect to the thin flat heat pipe with grooves as the capillary wick respectively. The possibility of using the wire bundle as a capillary wick in the heat pipe was validated in the present study; further study for commercializing this concept will be taken up in the future.

Cu-Filling Behavior in TSV with Positions in Wafer Level (Wafer 레벨에서의 위치에 따른 TSV의 Cu 충전거동)

  • Lee, Soon-Jae;Jang, Young-Joo;Lee, Jun-Hyeong;Jung, Jae-Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.4
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    • pp.91-96
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    • 2014
  • Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

Radio Frequency Circuit Module BGA(Ball Grid Array) (Radio Frequency 회로 모듈 BGA(Ball Grid Array) 패키지)

  • Kim, Dong-Young;Jung, Tae-Ho;Choi, Soon-Shin;Jee, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.8-18
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    • 2000
  • We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

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