• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.152-160
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• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

• Korean Chemical Engineering Research
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• v.56 no.4
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• pp.474-478
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• 2018

For process safety, fire and explosion characteristics of combustible materials handled at industrial fields must be available. The combustion properties for the prevention of the accidents in the work place are flash point, fire point, explosion limit, and autoignition temperature (AIT) etc.. However, the combustion properties suggested in the Material Safety Data Sheet (MSDS) are presented differently according to the literatures. The accurate combustion properties are necessary to safely treatment, transportation and handling of flammable substances. In the chemical industries, n-ethylaniline which is widely used as a raw material of intermediate products and rubber chemicals was selected. For safe handling of n-ethyl aniline, the flash point, the fire point and the AIT were measured. The lower explosion limit (LEL)of n-ethylaniline was calculated using the lower flash point obtained in the experiment. The flash points of n- ethylaniline by using the Setaflash and Pensky-Martens closed-cup testers measured $77^{\circ}C$ and $82^{\circ}C$, respectively. The flash points of n-ethylaniline using the Tag and Cleveland open cup testers are measured $85^{\circ}C$ and $92^{\circ}C$, respectively. The AIT of the measured n-ethyl aniline by the ASTM E659 apparatus was measured at $396^{\circ}C$. The LEL of n-ethylaniline measured by Setaflash closed-cup tester at $77^{\circ}C$ was calculated to be 1.02 vol%. In this study, it was possible to predict the LEL by using the lower flash point of n-ethylaniline measured by closed-cup tester. The relationship between the ignition temperature and the ignition delay time of the n-ethylaniline proposed in this study makes it possible to predict the ignition delay time at different ignition temperatures.

• Korean Journal of Construction Engineering and Management
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• v.13 no.3
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• pp.67-77
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• 2012

O Having a highly reliable plan for the process and estimating an accurate construction period during the early stages of a construction project can prevent falsifying the plan and reduce the occurrence of construction delays. Moreover, it allows a succession of swift and accurate decisions to happen. The difficulty in obtaining an accurate estimate of the construction period is especially prominent in high-rise building projects because the works involved are very complicated and costly. As such, it is important that research is done to find out the impacts a reliable plan and good estimate of the construction period can bring with regards to the monthly work efficiency and success of a high-rise building project. However, due to the difference in climatic conditions at high altitude and surface level, the current way of calculating work efficiency in a typical project is inaccurate for a high-rise building project. With that, this paper aims to compute the work efficiency with height, taking into consideration the change in climatic elements at different working heights. A comparison of the results according to the climatic features of each city can also be done in this paper. According to the results calculated in work altitudes, the work efficiency in Busan falls the most. On the other hands, the work efficiency in Seoul falls the least. The reason these results are shown is the influence of wind speed at high altitude. The estimation of work efficiency at high altitude would be used for estimating construction period, feasibility studies, and selecting a city of high-rise building projects.

• Polymer(Korea)
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• v.29 no.3
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• pp.288-293
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• 2005

Osmotic granule system which is one of the drug delivery systems has been developed to improve manufacturing process and other problems of tablet osmotic systems. It consists of water swellable seed layer, nifedipine drug layer, and drug release controlled membrane layer and manufactured by fluidized bed coater. The granule size and mombrane thickness can be controlled by various amounts of seed and coating solution, respectively. It could be observed that the morphology of osmotic granule was different at each coating step as well as type of coating solution. The bigger the size of granule, the slower the release rate was observed due to decreasing the total specific surface wed of granule. Also, it was observed that the increase of membrane thickness was caused to retard the dissolution of nifedipine due to decreasing the water absorption rate. The drug solubility for dissolution media is greatly affected to nifedipine release. From these results, we assured that osmotic granule can be fabricated by fluidized bed coating methods, and the appropriate release profile could be controlled by the controlling of bead size, membrane thickness and dissolution media.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• The Korean Society of Law and Medicine
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• v.20 no.1
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• pp.83-107
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• 2019

In order to resolve a dispute over a medical accident, the court is in the process of appraising the medical records for medical professionals to report their medical expertise or judgments using that knowledge. The consequences of expert opinion about a medical accident are only one of the methods of evidence as a reference. Therefore, in principle, the court should not be bound to the results, but the court, which is not a medical expert, can not completely rule out medical expert opinion as to whether there is medical malpractice and causality. Therefore, it can not be denied that the proportion of expert opinion of medical records in the dispute about medical accidents is high and it has an important influence on the judgement of the court. In this paper, we examine the significance and function of expert opinion of the medical accident, examine the appraising procedure of the medical records in the court and the appraising procedure of the medical accidents of the Korean medical dispute mediation arbitrator do. In addition, I would like to examine what kind of attitude is being taken in response to expert opinion of medical records in Korea to court, to examine the implications of the case of Japan as a foreign system, and to suggest improvement points in the expert opinion procedure of medical record filing in Korea. In particular, I would like to suggest improvements on issues such as the fairness of the expert opinion of medical records and the delays in litigation due to delays in the process of expert opinion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.1-9
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• 2009

A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.712-720
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• 2001

Algorithms from the research of the layout migration were proposed in the paper. These are automatic recognition algorithm for the VLSI devices from it, graph based construction algorithm to maintain the constraints, dependencies, and design rule between the devices, and high speed compaction algorithm to reduce size of the VLSI area and reuse the design with compacted size for the new technology. Also, this paper describes that why proposed algorithms are essential for the era of the SoC (System on a Chip), design reuse, and IP DB, which are the big concerns in these days. In addition to introduce our algorithms, the benchmark showed that our performance is superior by 27 times faster than that of the commercial one, and has better efficiency by 3 times in disk usage.