• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.775-778
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• 2000

2채널의 MPEG-2 Layer-Ⅲ 오디오 복호화 알고리듬이 16비트의 고정소수점 연산기로도 고음질의 오디오출력을 얻을 수 있도록 최적화를 수행하였다. 고음질을 얻기 위하여 고정소수점 연산기에서 발생하는 양자화 오차를 최소화 하였으며 각 복호화 과정 별로 최소의 오차를 발생시키는 알고리듬을 제안하고 사용하였다. 고정소수점 모의실험은 C-언어를 사용하여 수행되었으며, ISO-IEC 13818-4 Compliance Test를 수행하여 최적화된 복호화기가 ISO／IEC 13818-4 audio decoder의 기준을 만족함을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.49-59
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• 2008

SIFT(Scale Invariant Feature Transform) is an algorithm to extract vectors at pixels around keypoints, in which the pixel colors are very different from neighbors, such as vortices and edges of an object. The SIFT algorithm is being actively researched for various image processing applications including 3-D image constructions, and its most computation-intensive stage is a keypoint localization. In this paper, we develope a fixed-point model of the keypoint localization and propose its efficient hardware architecture for embedded applications. The bit-length of key variables are determined based on two performance measures: localization accuracy and error rate. Comparing with the original algorithm (implemented in Matlab), the accuracy and error rate of the proposed fixed point model are 93.57% and 2.72% respectively. In addition, we found that most of missing keypoints appeared at the edges of an object which are not very important in the case of keypoints matching. We estimate that the hardware implementation will give processing speed of $10{\sim}15\;frame/sec$, while its fixed point implementation on Pentium Core2Duo (2.13 GHz) and ARM9 (400 MHz) takes 10 seconds and one hour each to process a frame.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.53-56
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• 2004

본 논문은 HMM 기반 임베디드 음성인식 시스템 구현에 관한 몇 가지 주제들을 설명한다. 임베디드 환경은 한정된 자원을 가지고 있고 그러한 가운데 타당한 인식률과 향상된 인식 속도를 얻기 위해서 몇가지 방법들을 이 논문에서 설명한다. 구현 환경은 DSP6711 기반에서 이루어졌다. 가우시안 mixture 계산 루틴을 부동소수점 연산에서 고정소수점 연산 및 software pipelining을 적용하였다. 고정소수점 변환 전과 후 비슷한 인식률을 얻었고 고정소수점 변환과 software pipelining 적용 후 연산 속도의 향상을 얻었다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.08a
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• pp.121-126
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• 1998

고정 소수점 DSP 인 analog devices 사의 ADSP-2181을 이용하여 실시간 G.723.1 음성부호화기를 개발한 사례이다. G.723.1은 ITU에서 개발한 세계 표준 음성 부호화기로 낮은 전송율에서 고음질을 얻을 수 있다. 본 논문에서는 고정 소수점 DSP를 이용하여 부호화기를 갭라하는데 필요한 사항들을 제시하였다. 먼저 1절에서는 DAM성 부호화기의 특성에 대한 개괄을 설명하고, 2절에서는 G.723.1 부호화기의 특징을, 3절에서는 고정소수점 DSP를 이용하여 개발하는 과정을, 4절에서는 구현결과를 분석하였으며, 마지막으로 5절에서 결론을 맺는다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.95-117
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• 2006

In this paper, we describe the optimization of the link-level performance and the complexity of floating-point and fixed-point methods in IEEE 802.16e OFDMA/TDD mobile modem. In floating-point design, we propose the channel estimation methods for downlink traffic channel and select the optimized method using computer simulation. So we also propose efficent algorithms for time and frequency synchronization, Digital Front End and CINR estimation scheme to optimize the system performance. Furthermore, we describe fixed-point method of uplink traffic and control channels. The superiority of the proposed algorithm is validated using the performances of Detection, False Alarm, Missing Probability and Mean Acquisition Time, PER Curve, etc. For fixed-point design, we propose an efficient methodology for optimized fixed-point design from floating-point At last, we design fixed-point of traffic channel, time and frequency synchronization, DFE block in uplink and downlink. The tradeoff between performance and complexity are optimized through computer simulations.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.1
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• pp.95-103
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• 2009

We improve the performance of WCDMA repeater by cancelling the feedback interference radio signal under the fixed point implementation. Floating-point DSP or FPGA to implement the ICS algorithm may have an disadvantage of high cost, To solve this problem, we suggest the ICS algorithm based on LMS under fixed point operation, and show the validity of our results by comparing with the floating-point results through numerical simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1491-1497
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• 2004

The psychoacoustic model in MPEG audio layer-III (MP3) encoder is optimized for the fixed-point processing. The optimization process consists of determining the data word length of arithmetic unit and the algorithm for transcendental functions that are often used in the psychoacoustic model. In order to determine the data word length, we defined a statistical model expressing the relation between the fixed-point operation errors of the psychoacoustic model and the probability of alteration of the allocated bits doe to these errors. Based on the simulations using this model, we chose a 24-bit data path and constructed a 24-bit fixed-point MP3 encoder. Sound quality tests using the constructed fixed-point encoder showed a mean degradation of -0.2 on ITU-R 5-point audio impairment scale.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.457-458
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• 2013

본 논문은 Simulink 모델을 기반으로 하여 FPGA 알고리즘을 설계하는 과정을 구현하였다. Simulink 모델은 SRF-PLL 제어기법을 적용하였으며, Simulink 모델은 기본적으로 부동소수점으로 구성된다. 그러나 FPGA 구현에 필요한 VHDL 코드는 고정 소수점 변환이 필요하므로, 부동 소수점 모델을 고정 소수점으로 변환하고 두 연산 기법의 시뮬레이션 결과를 비교분석하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1460-1468
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• 2000

The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.

• ICROS
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• v.4 no.2
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• pp.18-19
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• 1998

이 글에서는 1. DSP 발전의 역사(Texas Instrument사의 DSP와 관련하여) 2. Texas Instrument TMS320 Family - 16고정소수점 DSP, 32 Bit 부동소수점 DSP 3. 앞으로의 전망 등에 대하여 다루었다.