• KSCI Review
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• v.15 no.1
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• pp.219-223
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• 2007

이 논문에서는 기존 개발된 일체형의 통합 터미널 보드의 유선방식으로 자동제어시스템에서의 중요 신호에 대한 전체적 통합관리시스템 구축을 위한 DCS터미널 원격 감시 보드를 설계 제작하고 제작된 보드의 동작을 테스트하기 위해 원격감시 프로그램을 구현하여 기능을 평가한다. 구현된 원격감시보드는 전원관리실의 각 릴레이들의 동작상태 및 릴레이와 퓨즈의 이상 유무를 실시간으로 확인이 가능하며 릴레이의 수명을 고려하여 릴레이의 고장을 사전에 예방함으로써 산업분야의 경제적인 효과가 기대된다.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.05a
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• pp.451-456
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• 1996

원자력발전소 설계업무 수행중 생산되는 전산데이타를 반영구적으로 보관하기 위하여 Autocom 장비를 이용한 마이크로피쉬(microfiche)를 생산해 왔으나 이 장비의 노후로 인한 잦은 고장 및 데이타의 재사용 불가로 인해 기기의 교체가 요구 되었다. 또한 영광 3호기 이후, 교체노심설계 및 핵연료 설계등의 원전 설계업무에 UNIX Workstation(W/S)이 사용되면서 UNIX 시스템의 네트웍을 이용한 온라인 데이타 저장의 필요성이 대두됨에 따라, 이에 대한 하드웨어 분석과 테스트 과정을 거쳐 분산 운영되는 UNIX 시스템에 적합한 CD-ROM 저장시스템을 구성하였다. 본 논문에서는 이러한 CD-ROM 저장 시스템의 기술적인 내용을 분석하고 향후 보완 및 개발되어야 할 내용을 제시하였다.

• Radiation Oncology Journal
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• v.23 no.3
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• pp.186-193
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• 2005

Purpose: To improve the management of a medical linear accelerator, the records of operational failures of a Varian CL2l00C over a ten year period were retrospectively analyzed. Materials and Methods: The failures were classified according to the involved functional subunits, with each class rated Into one of three levels depending on the operational conditions. The relationships between the failure rate and working ratio and between the failure rate and outside temperature were investigated. In addition, the average life time of the main part and the operating efficiency over the last 4 years were analyzed. Results: Among the recorded failures (total 587 failures), the most frequent failure was observed in the parts related with the collimation system, including the monitor chamber, which accounted for $20\%$ of all failures. With regard to the operational conditions, 2nd level of failures, which temporally interrupted treatments, were the most frequent. Third level of failures, which interrupted treatment for more than several hours, were mostly caused by the accelerating subunit. The number of failures was increased with number of treatments and operating time. The average life-times of the Klystron and Thyratron became shorter as the working ratio increased, and were 42 and $83\%$ of the expected values, respectively. The operating efficiency was maintained at $95\%$ or higher, but this value slightly decreased. There was no significant correlation between the number of failures and the outside temperature. Conclusion: The maintenance of detailed equipment problems and failures records over a long period of time can provide good knowledge of equipment function as well as the capability of predicting future failure. Wore rigorous equipment maintenance Is required for old medical linear accelerators for the advanced avoidance of serious failure and to improve the qualify of patient treatment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.54-60
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• 2007

This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.5
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• pp.507-513
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• 2008

In this paper, we present a development of an Avionics Hot Bench(AHB) used for the verification of operational flight programs and fault analysis using various simulation and stimulation software. We propose an application of the open system architecture to develop the AHB which can be used for the development of a real aircraft avionics system. In the design of the AHB, to reduce the development period and cost we use as many as commercial off-the-shelf hardware and software items. The developed AHB is compared with the existing proven AHB which was used for T-50 avionics system development. Thorough comparison between the test results using the developed AHB and those using the existing AHB is performed and the overall comparison results are very satisfactory.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.33-42
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• 2007

Accurate predictions of software release times, and estimation of the reliability and availability of a software product require quantification of a critical element of the software testing process : test coverage. This model called Enhanced non-homogeneous poission process(ENHPP). In this paper, exponential coverage and S-shaped model was reviewed, proposes the Kappa coverage model, which maked out efficiency application for software reliability. Algorithm to estimate the parameters used to maximum likelihood estimator and bisection method, model selection based on SSE statistics and Kolmogorov distance, for the sake of efficient model, was employed. From the analysis of mission time, the result of this comparative study shows the excellent performance of Burr coverage model rather than exponential coverage and S-shaped model using NTDS data. This analysis of failure data compared with the Kappa coverage model and the existing model(using arithmetic and Laplace trend tests, bias tests) is presented.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.3
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• pp.571-578
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• 2018

The deteriorated pipline often causes the unexpected leakage and crack. Negligence and late maintenance leads the enormous damage for gas and water resource. This paper proposes early fault detection and diagnosis algorithm for pipeline using acoustic emission (AE) signals. Early fault detection method for pipeline compares the frequency amplitude of the spectrum to that of the spectrum in normal condition. Larger amplitude of the spectrum indicates abnormal condition. Early fault diagnosis algorithm uses support vector machines (SVM), which is trained for normal and abnormal conditions to diagnose the measured AE signal from the target pipeline. In the experiment, a pipeline testbed is constructed similarly to real industrial pipeline. Normal, 5mm cracked, 10mm holed pipelines are installed and tested in this study. The proposed fault detection and diagnosis technique is validated as an efficient approach to detect early faulty condition of pipeline.

• Journal of Korean Society for Quality Management
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• v.17 no.2
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• pp.17-26
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• 1989

This paper is concerned with forecasting the existing number of errors in the computer software and optimizing the stopping time of the software test based upon the forecasted number of errors. The most commonly used models have assessed software reliability under the assumption that the software failure late is proportional to the current fault content of the software but invariant to time since software faults are independents of others and equally likely to cause a failure during testing. In practice, it has been observed that in many situations, the failure rate decrease. Hence, this paper proposes a mathematical model to describe testing situations where the failure rate of software limearly decreases proportional to testing time. The least square method is used to estimate parameters of the mathematical model. A cost model to optimize the software testing time is also proposed. In this cost mode two cost factors are considered. The first cost is to test execution cost directly proportional to test time and the second cost is the failure cost incurred after delivery of the software to user. The failure cost is assumed to be proportional to the number of errors remained in the software at the test stopping time. The optimal stopping time is determined to minimize the total cost, which is the sum of test execution cast and the failure cost. A numerical example is solved to illustrate the proposed procedure.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.30-38
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• 2003

UDP library of Verilog HDL has been used for simulation of digital systems. But it takes a lot of time and efforts to generate a gate-level library equivalent to the UDP library manually due to the characteristic of UDP that does not support synthesis. It is indispensable to generate equivalent gate-level model in testing the digital systems because fault coverage can be reduced without the equivalent gate-level models. So, it is needed to automate the process of generating the equivalent gate-level models. An algorithm to solve this problem has been proposed, but it is unnecessarily complex and time-consuming. This paper suggests a new improved algorithm to implement the conversion to gate-level models, which exploits the characteristic of UDP Experimental results are demonstrated to show the effectiveness of the new algorithm.