• Title/Summary/Keyword: 고장모드분석

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A Study for Accelerated Life Testing and Failure Analysis of Chip Varistor (Varistor 의 ALT(Accelerated Life Testing) 설계 및 주 고장모드 분석)

  • Chang Woo-Sung;Lee Jun-Hyuk;Lee Kwan-Hun;Oh Young-Hwan
    • Proceedings of the Korean Reliability Society Conference
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    • 2005.06a
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    • pp.51-67
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    • 2005
  • General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide sed electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mope caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

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원전 계측제어 고신뢰도 소프트웨어 확인/검증 기술 현황

  • 이장수;권기춘;동인숙
    • Nuclear Engineering and Technology
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    • v.26 no.4
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    • pp.600-610
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    • 1994
  • 원자력산업계에서는 원전 계측제어계통의 디지털화를 위해 많은 노력을 기울이고 있으나, 원자력산업의 특수성인 시스템 안전성 확보에 필요한 소프트웨어 개발기준과 규제방법이 정립되지 못하고 있다. 뿐만 아니라 디지털 계측제어계통의 핵심 기반기술인 고신뢰도 소프트웨어 개발 방법론이 확립되지 못하여 소프트웨어 공통모드고장 문제, 정량적인 소프트웨어 신뢰도 보장 문제 등이 논란의 대상이 되고 있다. 이와 같이 원전 계측제어계통 디지털화 성공을 위해서는 소프트웨어 신뢰도 확보가 관건이며 고신뢰도 소프트웨어 확인 및 검증 기술 개발이 절실히 요구된다. 본 기술보고에서는 디지털 계측제어계통 소프트웨어에 대한 규제요건을 소프트웨어 신뢰도 보장을 위한 개발자, 사용자, 규제자 사이의 합의 기준측면에서 분석하였다. 또한 최근의 미국 원자력규제위원회의 디지털 계측제어계통 소프트웨어에 대한 규제방법과 규제동향을 살펴보았으며 마지막으로 고신뢰도 소프트웨어 개발과 확인 및 검증 방법, 규제 요건, 규제 방법 등에서 공통적으로 고려해야 할 기술적 측면의 현안과 이의 해결을 위한 연구 현황등을 파악하였다.

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A Development Guideline for MMIS Software Applications in Nuclear Power Plants (원전 MMIS 소프트웨어 응용을 위한 개발 지침에 관한 연구)

  • Lee, Jong-Bok;Suh, Yong-Suk;Suh, Sang-Moon;Park, Geun-Ok
    • Annual Conference of KIPS
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    • 2004.05a
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    • pp.293-296
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    • 2004
  • 원자력 산업계에서는 원전 MMIS(Man-Machine Interface System)의 디지털 기술 적용을 위해 많은 노력을 기울이고 있고, 디지털 MMIS의 핵심기반기술인 고 신뢰도 소프트웨어 개발 방법론이 확립되지 못하여 소프트웨어 공통모드고장 문제, 정량적인 소프트웨어 신뢰도 보장 문제 등이 현안으로 제기되고 있다. 이에 따라 원자력 산업의 특수성인 안전성 확보에 필요한 개발기준과 규제방법 정립에 많은 연구가 수행되고 있다. 또한 이와 같이 원전 MMIS의 디지털화를 성공하기 위해서는 소프트웨어의 고 신뢰도 확보가 관건이며, 고 신뢰도와 품질을 확보하기 위한 소프트웨어 개발 지침의 정립이 요구되고 있다. 본 논문에서는 원전 소프트웨어 개발에 적용되는 규제 요건을 분석하고, SMART(System-integrated Modular Advanced ReacTor) MMIS 소프트웨어 개발에 적용될 소프트웨어 개발 지침을 제시한다

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A Study of Hazard Analysis and Monitoring Concepts of Autonomous Vehicles Based on V2V Communication System at Non-signalized Intersections (비신호 교차로 상황에서 V2V 기반 자율주행차의 위험성 분석 및 모니터링 컨셉 연구)

  • Baek, Yun-soek;Shin, Seong-geun;Ahn, Dae-ryong;Lee, Hyuck-kee;Moon, Byoung-joon;Kim, Sung-sub;Cho, Seong-woo
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.19 no.6
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    • pp.222-234
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    • 2020
  • Autonomous vehicles are equipped with a wide rage of sensors such as GPS, RADAR, LIDAR, camera, IMU, etc. and are driven by recognizing and judging various transportation systems at intersections in the city. The accident ratio of the intersection of the autonomous vehicles is 88% of all accidents due to the limitation of prediction and judgment of an area outside the sensing distance. Not only research on non-signalized intersection collision avoidance strategies through V2V and V2I is underway, but also research on safe intersection driving in failure situations is underway, but verification and fragments through simple intersection scenarios Only typical V2V failures are presented. In this paper, we analyzed the architecture of the V2V module, analyzed the causal factors for each V2V module, and defined the failure mode. We presented intersection scenarios for various road conditions and traffic volumes. we used the ISO-26262 Part3 Process and performed HARA (Hazard Analysis and Risk Assessment) to analyze the risk of autonomous vehicle based on the simulation. We presented ASIL, which is the result of risk analysis, proposed a monitoring concept for each component of the V2V module, and presented monitoring coverage.

Vulnerability Assessment Procedure for the Warship Including the Effect of Shotline and Penetration of Fragments (탄두의 관통 효과를 고려한 함정 취약성 평가 절차에 관한 기본 연구)

  • Kim, Kwang-Sik;Lee, Jang-Hyun
    • Journal of the Society of Naval Architects of Korea
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    • v.49 no.3
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    • pp.254-263
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    • 2012
  • The survivability of warship is assessed by susceptibility, vulnerability and recoverability. Essentially, a vulnerability assessment is a measure of the effectiveness of a warship to resist hostile weapon effects. Considering the shot line and its penetration effect on the warship, present study introduces the procedural aspects of vulnerability assessments of warship. Present study also considers the prediction of penetration damage to a target caused by the impact of projectiles. It reflects the interaction between the weapon and the target from a perspective of vulnerable area method and COVART model. The shotline and tracing calculation have been directly integrated into the vulnerability assessment method based on the penetration equation empirically obtained. A simplified geometric description of the desired target and specification of a threat type is incorporated with the penetration effect. This study describes how to expand the vulnerable area assessment method to the penetration effect. Finally, an example shows that the proposed method can provide the vulnerability parameters of the warship or its component under threat being hit through tracing the shotline path thereby enabling the vulnerability calculation. In addition, the proposed procedure enabling the calculation of the component's multi-hit vulnerability introduces a propulsion system in dealing with redundant Non-overlapping components.

A FPGA Implementation of BIST Design for the Batch Testing (일괄검사를 위한 BIST 설계의 FPGA 구현)

  • Rhee, Kang-Hyeon
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.7
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    • pp.1900-1906
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    • 1997
  • In this paper, the efficient BILBO(named EBILBO) is designed for BIST that is able to batch the testing when circuit is designed on FPGA. The proposed algorithm of batch testing is able to test the normal operation speed with one-pin-count that can control all part of large and complex circuit. PRTPG is used for the test pattern and MISR is used for PSA. The proposed algorithm of batch testing is VHDL coding on behavioral description, so it is easily modified the model of test pattern generation, signature analysis and compression. The EBILBO's area and the performance of designed BIST are evaluated with ISCAS89 benchmark circuit on FPGA. In circuit with above 600 cells, it is shown that area is reduced below 30%, test pattern is flexibly generated about 500K and the fault coverage is from 88.3% to 100%. EBILBO for the proposed batch testing BIST is able to execute concurrently normal and test mode operation in real time to the number of $s+n+(2^s/2^p-1)$ clock(where, in CUT, # of PI;n, # of register, p is order # of polynomial). The proposed algorithm coded with VHDL is made of library, then it well be widely applied to DFT that satisfy the design and test field on sme time.

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Verification of “dual-master” Duplication Flight Control System using Simulink Virtual Module (Simulink 가상모듈을 이용한 “dual-master” 이중구조 비행제어시스템 검증)

  • Kim, Sung-Su;Kim, Sung-Hwan;Jang, Se-Ah;Choi, Kee-Young;Park, Choon-Bae;Rhee, Ihn-Seok;Ha, Cheol-Keun
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.9
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    • pp.867-873
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    • 2008
  • Model based virtual Flight Control System construction is essential for Fly-by-Wire Flight Control System verification & validation(V&V) of concurrent engineering base. We researched the concept of dual-architecture system for virtual system construction, and analyzed Flight Control System that is applied to high altitude long endurance(HAE) UAS. Finally, we constructed the model based virtual Flight Control System with system analysis and achieved system verification about flight critical failure modes. Analysis target is RQ-4A.

Accelerated Life Test and Analysis of Track Drive Unit for an Excavator (주행 구동 유니트의 가속 수명 시험 및 분석)

  • Lee Y.B.;Park J.H.
    • Transactions of The Korea Fluid Power Systems Society
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    • v.2 no.2
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    • pp.1-7
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    • 2005
  • For the reliability evaluation of the track drive unit(TDU), firstly, we analyzed the major failure modes through FMEA(failure mode & effects analysis), FTA(failure tree analysis), and 2-stage QFD(quality function deployment), and then quantitatively determined the priority order of test items. The Minitab analysis was also performed for prediction of life distribution and parameters of TDU by use of field failure data collected from 430 excavators for two years. In addition, we converted the fluctuation load in field conditions into the equivalent load, and for evaluation of the accelerated lift by the cumulative fatigues, the equivalent load is again divided into the fluctuation load by reference of test time. And then, by use of the test method in this paper, the acceleration factor(AF) of needle bearing inside planetary gear which is the most weakly designed part of TDU is achieved as 5.3. This paper presents the quantitative selection method of test items for reliability evaluation, the determination method of the accelerated life test time, and the method of non-failure test time based on a few of samples. And, we proved the propriety of the proposed methods by experiments using a TDU for a 30 ton excavator.

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Improvement of the Differential Current Relaying Method for Protecting the Transmission Line Equipped with UPFC (UPFC를 포함한 송전성에서의 전류차동 보호 방식의 개선)

  • Lim, Jung-Uk;Kwon, Young-Jin;Runolfsson, Thordur
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.8
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    • pp.40-47
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    • 2005
  • The objective of this paper is to analyze power system dynamics influenced by UPFC(Unified Power flow Controller) operation and to develop a refined DCRM(Differential Current Relaying Method) to protect the transmission line with UPFC effectively. The implementation of control strategies for UPFC introduces new power system dynamic problems that must be considered while applying the conventional DCRM. In this paper, impact of UPFC operation on the DCRM has been reviewed and a refined DCRM has been proposed to detect faults properly in spite of UPFC operation. The porposed method is verified by simulation on the line-faulted system with UPFC.

FMEA for CNS Facility and Cause Analysis of Shutdown Events to Improve Reactor Availability (원자로 이용률 향상을 위한 냉중성자원 시설의 고장모드영향분석 및 정지이력의 원인분석)

  • Lee, Yoon-Hwan;Hwang, Jeong Sik
    • Journal of the Korean Society of Safety
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    • v.35 no.5
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    • pp.115-120
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    • 2020
  • From 2009 when the CNS facility was installed, the number of reactor failures due to abnormal CNS facility system has increased significantly. Of the total of 19 nuclear reactor shutdowns over the six years from 2009 to 2019, there were 10 nuclear reactor shutdowns associated with the CNS facility, which are very numerous. Therefore, this report intends to analyze the history of nuclear reactor shutdowns due to CNS facility system failure in detail, and to present the root cause and solution to problems. As a result of FMEA implementation of CNS facility system, a total of 76 SPVs were selected. In addition, 10 cases of reactor shutdown history due to CNS facility system abnormalities were analyzed in detailed, and improvement plans for solving the root cause and problem were suggested for each trip history. The results of this study are expected to be able to operate the domestic research reactor and CNS facilities more stably by providing effective measures to prevent recurrence of CNS facilities and reactor trips.