• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.563-564
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• 2017

The core of the cloud computing technology is the data center in that the networking technology is important. Cloud data centers are comprised of tens or even hundreds of thousands of physical servers, so networking technology is required for high-speed data transfer. These networking technologies also require scalability, fault tolerance, and agility. For these requirements, many multi-path based schemes have been proposed. However, it was mainly used for load balancing of traffic and select a path randomly. In this paper, a scheme that can construct a multipath using software defined networking technology and transmit the traffic in parallel by using the multipath to achieve a fast transmission speed, solve the scalability problem and fault tolerance is proposed.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1756-1769
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• 1999

Parallel paths in an interconnection network have some significance in that message transmission time can be reduced because message is divided into packets and transmitted in parallel through several paths, and also an whose nodes has 2n binary bit string, is an interconnection network which has a lower network cost than hypercube and its variation. In this paper, we analyze node disjoint parallel path in Folded Hyper-Star graph FHS(2n,n) proposed as the topology of parallel computers and, using the result, prove that the fault diameter of a Folded Hyper-Star graph FHS(2n,n) is 2n-1.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.6
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• pp.629-633
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• 2011

Recently, systems such as aircraft, trains and ships have become larger more complex. Therefore, the reliability calculation of these systems is more difficult. This paper presents a reliability calculation algorithm for a complex system with a solution that is difficult to analyze. When the system has a very complex structure, it is very difficult to find an analytical solution. In this case, we can assess system reliability using the failure enumeration method of the reliability path. In this research, we represent the reliability block diagram by an adjacent matrix and define the reliability path. We can find any system status by the failure enumeration of the reliability path, and thus we can calculate any kind of system reliability through this process. This result can be applied to RCM (Reliability-Centered Maintenance) and reliability information-management systems, in which the system reliability is composed of the reliabilities of individual parts.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.153-156
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• 2003

본 논문에서는 첫 행과 마지막 행에 추가 링크를 갖는 $m{\times}n$ 메쉬 연결망 $M_{2}(m,\;n)$의 고장 해밀톤 성질을 고려한다. 이분 그래프인 $M_{2}(m,\;n)$에 하나의 결함 링크가 발생하더라도 임의의 두 노드가 다른(같은) 집합에 속한 경우 두 노드를 잇는 길이 mn - 1(mn - 2)인 경로가 존재함을 보인다. 또한 하나의 결함 노드 또는 링크가 있는 경우 임의의 두 노드를 잇는 적어도 길이 mn - 4인 경로가 존재함을 보인다. 이러한 결과들을 이용하여 짝수개의 노드를 갖는 3차원 메쉬의 고장 해밀톤 성질을 보인다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1996.10a
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• pp.106-110
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• 1996

고밀도 집적회로(VLSI)의 설계 과정에 있어 테스트(test)는 매우 중요한 과정으로서, 회로내의 결함(fault)을 찾기 위해 일련의 입력값을 넣어 그 출력값으로 고장 여부를 판단한다. 회로의 테스트를 위하여 사용되는 일련의 입력값을 테스트패턴(test pattern)이라 하며 최고 2n개의 테스트패턴이 생성될 수 있다. 그러므로 얼마나 작은 테스트패턴을 사용하여 회로의 결함 여부를 판단하느냐가 주된 관점이 된다. 기존의 테스트 패턴 생성 알고리즘인 휴리스틱(heuristic)조건에서 가장 큰 문제점은 빈번히 발생하는 백트랙(backtrack)과 이로 인한 시간과 기억장소의 낭비이다. 본 논문에서는 이러한 문제점을 보완하기 위해 퍼지 기법을 이용한 새로운 알고리즘을 제안한다. 제안된 기법에서는 고장신호 전파과정에서 여러개의 전파경로가 존재할 때, 가장 효율적인 경로를 선택하는 단계에서 퍼지 관계곱(Fuzzy Relational Product)을 이용한다. 이 퍼지 기법은 백트랙 수를 줄이고 기억장소와 시간의 낭비를 줄여 테스트 패턴 생성의 효율을 증가시킨다.

• Journal of KIISE:Information Networking
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• v.27 no.2
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• pp.187-196
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• 2000

Failures in ATM networks can occur at virtual path (VP) links, virtual path switches, and virtual channel (VC) switches. Restoration schemes have been proposed for VP link and VP switch failures, however, none for VC switch failures. In general, VC switches are used for edge nodes in protection domains. Since even only one VC switch failure can cause a critical problem, new restoration schemes for VC switch failures are highly required. Restoration schemes at the VP level proposed so far can be categorized into those using the flooding algorithm and those using the backup virtual path (BVP) concept. Even though the latter cannot handle unpredictable failures, it has some advantages such as fast restoration and low spare capacity requirement. In this paper, we propose new restoration schemes using a new type of BVPs to handle VC switch failures. The simulation results show that the proposed schemes can restore virtual connection failures due to VC switch failures without degrading restorability for VP failures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1631-1642
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• 1999

In this paper, we propose a new fault tolerant ATM Switch and a new adaptive self-routing scheme used to make the switch to be fault tolerant. It can provide more multiple paths than the related previous switches between an input/output pair of a switch by adding extra links between switching elements in the same stage and extending the self-routing scheme of the Banyan network. Our routing scheme is as simple as that of the banyan network, which is based on the topological relationships among the switching elements (SE’s) that render a packet to the same destination with the regular self-routing. These topological properties of the Banyan network are discovered in this paper. We present an algebraic proof to show the correctness of this scheme, and an analytic reliability analysis to provide quantitative comparisons with other switches, which shows that the new switch is more cost effective than the Banyan network and other augmented MIN’s in terms of the reliability.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.66-75
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• 2016

Due to aggressive scaling of device sizes and reduced noise margins, physical defects caused by aging and process variation are continuously increasing. Additionally, with scaling limitation of metal wire and the increasing of communication volume, fault tolerant method in manycore network-on-chip (NoC) has been actively researched. However, there are few researches investigating reliability in NoC with voltage-frequency-island (VFI) regime. In this paper, we propose a table-based routing technique that can communicate, even if link failures occur in the VFI NoC. The output port is alternatively selected between best and the detour routing path in order to improve reliability with minimized hardware cost. Experimental results show that the proposed method achieves full coverage within 1% faulty links. Compared to $d^2$-LBDR that also considers a routing method for searching a detour path in real time, the proposed method, on average, produces 0.8% savings in execution time and 15.9% savings in energy consumption.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.225-232
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• 2011

Restricted Hypercube-Like (RHL) graphs are a graph class that widely includes useful interconnection networks such as crossed cube, Mobius cube, Mcube, twisted cube, locally twisted cube, multiply twisted cube, and generalized twisted cube. In this paper, we show that for an m-dimensional RHL graph G, $m{\geq}4$, with an arbitrary faulty edge set $F{\subset}E(G)$, ${\mid}F{\mid}{\leq}m-2$, graph $G{\setminus}F$ has a hamiltonian path between any distinct two nodes s and t if dist(s, V(F))${\neq}1$ or dist(t, V(F))${\neq}1$. Graph $G{\setminus}F$ is the graph G whose faulty edges are removed. Set V(F) is the end vertex set of the edges in F and dist(v, V(F)) is the minimum distance between vertex v and the vertices in V(F).

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.