Partial Enhanced Scan Method for Path Delay Fault Testing

경로 지연 고장 테스팅을 위한 부분 확장 주사방법

  • 김원기 (삼성전기) ;
  • 김명균 (연세대학교 대학원 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과) ;
  • 한건희 (연세대학교 전기전자공학과)
  • Published : 2000.10.01

Abstract

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

반도체 집적 회로가 점점 복잡해지고 고속화되면서 반도체 집적 회로의 동작에 대한 검사 뿐 아니라, 회로가 원하는 시간 내에 동작함을 보장하는 지연 고장 검사의 중요성이 점점 커지고 있다. 본 논문에서는 경로 지연 고장에 대한 효율적인 테스트 입력 생성을 위하여 새로운 부분 확장 주사 방법을 제안한다. 본 논문에서는 유추와 할당을 적용한 테스트 입력 자동 생성기를 기반으로 하여 새로운 부분 주사 방법을 구현하였다. 우선적으로 표준 주사환경에서 테스트 입력을 생성한 후에 테스트 입력이 제대로 생성되지 않은 주사 사슬에 대하여 테스트 입력 생성기를 수행하는 동안의 정보를 이용하여 확장 주사 플립플롭이 적용될 플립플롭을 결정하였다. 확장 주사 플립플롭을 결정하는 기준으로서는 고장 검출율과 하드웨어 오버헤드를 사용하였다. 순차 회로인 ISCAS 89 벤치 마크 회로를 이용하여 실험을 수행하였으며, 실험을 통하여 표준 주사와 확장 주사 환경, 부분 확장 주사 환경에서 고장 검출율을 비교, 확인하였다. 그리고 새로운 알고리즘이 적용된 부분 확장 주사 방법에서 높은 고장 검출율을 확인함으로써 효율성을 입증하였다.

Keywords

References

  1. V. Iyengar, B. Rosen, and I. Spillinger, 'Delay Test Generation Algebra and Algorithms,' Proc. of International Test Conference, pp.867-876, 1988 https://doi.org/10.1109/TEST.1988.207874
  2. J. Warwkauski E. Lindbloom, B. Rosen and V. Iyengar, 'Transition fault simulation,' IEEE Design and Test of Computer, pp.32-38, April 1987 https://doi.org/10.1109/MDT.1987.295104
  3. G. L. Smith, 'Model for delay faults based upon paths,' Proc. of International Test Conference, pp. 342-349, 1985
  4. C. Lin and S. Reddy, 'On Delay Fault Testing in Logic Circuit,' IEEE Trans. on Computer, pp 694-703, Step. 1987
  5. M Schulz et al, 'Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults,' Proc. of Fault Tolerant Computing Symposium, pp.44-51, 1989 https://doi.org/10.1109/FTCS.1989.105541
  6. B. Underwood, S. Kang, and O. Law, 'A Path-Delay Test Generator for Large VLSI Circuits,' Proc. of International Conference on VLSI and CAD, pp. 368-371, 1993
  7. S. Kang, B. Underwood and W Law, 'Path Delay Fault Simulation for a Standard Scan Design Methodology,' Proc. of International Conference on Computer Design, pp.359-362, 1994 https://doi.org/10.1109/ICCD.1994.331926
  8. Bill Underwood, Wai-On Law, Sungho Kang, Haluk Konuk, 'Fastpath : A Path-Delay Test Generator for Standard Scan Design,' Proc. of International Test Conference, pp.154-163, 1994 https://doi.org/10.1109/TEST.1994.527946
  9. Prab Varma, 'On Path Delay Testing in a Standard Scan Environments,' Proc of International Test Conference, pp.164-173, 1994 https://doi.org/10.1109/TEST.1994.527947
  10. S. Devadas and K. Kcutzer, 'Design of Integrated Circuits Fully Testable for Delay Faults and Multi-faults,' Proc. of International Test Conference, pp 284-293, 1990 https://doi.org/10.1109/TEST.1990.114034
  11. S. Devadas and K. Keutzer, 'Synthesis and Optimization Procedure for Robustly Delay-Fault Testable Logic Circuits,' Proc. of the 27th Design Automation Conference, pp.221-227, June 1990 https://doi.org/10.1109/DAC.1990.114858
  12. V. Chickermane and J. H. Patel, 'An optimization based approach to the partial scan design problem,' Proc. of International Test Conference, pp.377-386, 1990 https://doi.org/10.1109/TEST.1990.114045
  13. R. Gupta and M. A. Breuer, 'Ballast: A methodology for partial scan design,' Proc. of the Fault Tolerant Computing Symposium, 1989 https://doi.org/10.1109/FTCS.1989.105553
  14. V, Boppana and W Kent Fuchs, 'Partial scan design based on state transition modeling,' Proc. of International Test Conference. pp,538-547, 1996 https://doi.org/10.1109/TEST.1996.557079
  15. D Xiang and J. H. Patel, 'A Global algorithm for the partial scan design problem using circuit state information,' Proc. of International Test Conference, pp.548-557, 1996 https://doi.org/10.1109/TEST.1996.557081
  16. V, D Agrawal, K. T. Cheng, D. D Johnson, and T. Lin, 'Designing circuits with partial scan,' IEEE Design and Test of Computers, Vol.5, April 1988 https://doi.org/10.1109/54.2032
  17. I. Park, D. S Ha, and G. Sim, 'A new method for partial scan design based on propagation and justification requirements of fault,' Proc. of International Test Conference, pp.413-422, 1995 https://doi.org/10.1109/TEST.1995.529867
  18. K T Cheng, S. Devadas, and K. Keulzer, 'A Partial enhanced-scan approach to Robust delay fault test generation for sequential circuits,' Proc. of International Test Conference, pp.403-410, 1991