• Journal of IKEEE
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• v.24 no.2
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• pp.486-491
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• 2020

ARM Cortex-M0 DesignStart provided by ARM is cost-free design development suit targeting for designing and prototyping SoC with Cortex-M0 core. In this paper, we presents a method how to implement a custom system design using ARM Cortex-M0 DesignStart. First, hardware elements for ARM Cortex-M0 DesginStart is analyzed focusing on bus and memory map, and next software toolchain is explained to clarify the translating process from high level language to binary machine language. As an example of the custom system, UART system operated with Cortex-M0 is designed and simulated.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.510-519
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• 2013

In this paper, we propose a voice-annotation browsing system that make the reading-disabled people to be able to find and play the existing voice-annotations. The proposed system consists of 4 steps: input, ranking & recommendation, search, and output. For the reading-disabled people depending only on the auditory sense, all steps can accept voice commands. To evaluate the effectiveness of our system, we design and implement an android-based mobile e-book application supporting the voice-annotation browsing ability. The implemented system is tested by a number of blind-folded users. As a result, we can see almost all the reading-disabled people can successfully and easily reach the existing voice-annotations they want to find.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.374-377
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• 2012

GNSS(Global Navigation Satellite System) based land transportation infrastructure system is consists of receiving station and central station. The functions of the central system include receiving station's data gathering and decoding, carrier correction and integrity information generated, transmission of data in real-time. In general, The central station architecture should take into account various important points relating to hardware/software of system, data archiving and checking, availability and continuity of operation, etc. There is a fundamental need for a generic design capable of being used in any situation. Also, There is need to develop an expandable and interoperable central station architecture. In this paper, the process of design and manufacture and verification will be introduced.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.288-295
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• 2005

Multi-signcryption scheme is an extension of signcryption scheme for multi-signers performing together the signcryption operation on messages, and it provides useful cryptographic functions such as confidentiality and authenticity for the sound circulation of messages through the Internet. In this paper, we show the weaknesses of the previous multi-signcryption schemes. And then we propose a new multi-signcryption scheme that improves the weaknesses and the efficiency of the previous schemes. Our scheme efficiently provides message flexibility, order flexibility, message verifiability, order verifiability, message confidentiality, message unforgeability, non-repudiation and robustness. Therefore, it is suitable for protecting messages and multi-signers from malicious attacks in the Internet.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.494-503
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• 2003

In this paper, we propose the implementation techniques of IC card chipset that is compatible with international standard ISO-7816 and supports WindowsCE operating system to expropriate various electronic cash and credit card. This IC card interface chip set is composed with 32 bit ARM720T Core and AES(Advanced Encryption System) cryptography module for electronic commerce. Six IC card interfaces support T=0, T=1 protocol and two of them are used to interface with user card directly, the others are used for interface with SAM card. In addition, It supports a LCD controller and USB interface for host. We improved the performance about 70% than software based It card chip set and verified using Hynix 0.35um process.

• Annual Conference of KIPS
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• 2005.05a
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• pp.671-674
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• 2005

현재 지능형 웹 서비스를 위한 서비스 온톨로지의 생성은 서비스 개발자의 휴리스틱에 의존하여 많은 시간과 비용을 소모할 뿐만 아니라 서비스와 서비스 온톨로지간의 완벽한 매핑이 어렵다는 문제점을 가지고 있다. 또한 서비스 온톨로지를 기술하기 위한 마크업 언어를 서비스 개발자가 단기간 내에 학습하기에 많은 어려움이 있는 실정이다. 본 논문에서는 지능형 웹 서비스를 위한 서비스 온톨로지 생성의 문제점들을 해결하기 위해 MDA 방법론을 사용하여 서비스 온톨로지를 효율적으로 설계 및 생성하기 위한 방안을 제안한다. 본 논문에서 제안하는 방안은 MDA를 기반으로 널리 사용되고 있는 UML을 사용하여 웹 서비스 모델을 설계하고 이를 OWL-S에 최적화된 모델로 변환한 후 XMI를 통해 OWL-S로 기술되는 서비스 온톨로지로 변환한다. 본 논문에서 제안하는 방안은 이미 널리 사용되는 UML과 같은 소프트웨어 공학적 방법을 사용하기 때문에 서비스 개발자들이 쉽게 서비스 온톨로지를 구축할 수 있으며 하나의 모델로부터 서비스와 서비스 온톨로지 모델을 동시에 이끌어 낼 수 있는 장점을 가진다. 또한 모델로부터 자동적으로 서비스 온톨로지를 생성함으로써 시간과 비용을 절감할 수 있는 효과를 얻을 수 있다. 그리고 플랫폼 변화와 같은 외부 환경 변화에 유연하게 대처할 수 있다. 끝으로 본 논문에서는 제안된 방안의 타당성을 검증하기 위해 실제로 웹 서비스 모델을 설계하고 서비스 온톨로지를 생성하는 예를 보인다. 또한 생성된 서비스 온톨로지가 올바르게 생성되었는지를 유효성 검사를 통해 검증한다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.8
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• pp.813-822
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• 2010

Integrated data processing for display of flight critical data and mission critical data was conducted without additional display instruments using glass cockpit design. Based on a pre-designed flight critical system and a mission critical system, this paper shows an optimal design of subsystem integration. The design satisfies safety requirements of flight control systems(FCS) and requires minimized modification of pre-designed systems. By conducting integration test using System Integration laboratory(SIL), it is confirmed that the introduced design approach meets the safety requirements of the MEP system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.46-53
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• 2008

This paper presents a 13.56 MHz RFID reader that can be used as a door-lock system for smart home security. The RFID reader consists of a transmitter, a receiver, and a data processing block. To verify the operation of the developed RFID reader, we present both a PSPICE simulation for transmitter/receiver and a digital simulation for data processing block. In particular, a CRC block for error detection of received data and a Manchester decoding block for position detection of collided data are designed using VHDL. In addition, we applied a binary search algorithm for multi-tag anti-collision. The anti-collision procedure is carried out by PIC microcontroller on software. The experimental results show that the developed reader can provide the right multi-tag recognition.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.564-566
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• 2003

전력 계통에서 안정한 전력을 공급하는 것은 매우 중요하다. 전력 계통의 오류는 전압 및 주파수를 감시함으로써 검출 가능하다. 본 논문에서는 디지털 위상 고정 루프를 이용한 전력 계통의 주파수 측정 장치를 제안하고 이를 구현한 결과를 제시하고자 한다. 제안한 주파수 측정 장치는 위상 고정 루프의 기본요소로 구성된다. 위상분별기는 배타적 논리연산을 통해 위상오차를 검출하고 위상의 앞섬 및 뒤짐의 검출이 가능하도록 설계하였으며, 전력 계통의 주파수 동특성을 고려해서 3차의 루프 필터를 설계하였다. DCO는 출력 주파수의 분해능을 고려하여 입력 신호를 정확하게 추정할 수 있도록 설계하였다. 제안한 주파수 측정 장치의 성능을 검증하기 위하여 모의실험을 통해 주파수 변동량의 측정 범위 및 정확도를 검토하였으며, FPGA와 CPU를 포함하는 하드웨어를 구현하였다. FPGA에는 Verilog HDL로 디지털 위상 고정 루프의 위상분별기와 DCO를 구현하였으며 루프필터는 소프트웨어로 구현하였다. 제안한 디지털 위상 고정 루프의 성능 검증을 위해 정밀한 함수 발생기의 출력을 인가한 후 출력 주파수를 측정한 결과 및 전력 계통에 대한 실험 결과를 제시하였다.