• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.38-49
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• 2001

This paper presents a new voltage down converter(VDC) using charge and discharge current adjustment circuitry that provides high frequency application. This VDC consist of a common driving circuit and compensation circuits: 2 sensors and each driving transistors for controlling gate current of driving transistor. These sensors are operated as adaptive biasing method with high speed and low power consumption. This circuit is designed with a $0.62{\mu}m$ N well CMOS technology. In H-spice simulation results, internal voltage is bounded ( IV, +0.6V) in proposed circuitry when load current rapidly increases and decreases during Gns between 0 and $200m{\Lambda}$. And the recovery time of internal voltage is about 7ns and 10ns when load current increases and decreases respectively. That is fast better than common driving circuit. Total power consumption is about 1.2mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.40-48
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• 1998

An offset compensation scheme for rail-to-rail CMOS op-amps with complementary input stages is presented. Two auxiliary amplifiers are used to compensate for the offsets of NMOS and PMOS differential input stages, and ping-pong control is employed for continuous-time operation. A 3V offset-compensated rail-to-rail CMOS op-amp has been designed and fabricated using a 0.8$\mu\textrm{m}$ single-poly, double-metal CMOS process. Measurement results show that offsets are reduced about 20 times by this scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.143-152
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• 2004

A novel low-power wideband bipolar second-generation current conveyors(CCIIs) and its application to universal instrumentation amplifier(UIA) were proposed. The CCII for accuracy voltage or current transfer characteristics and low current input impedance adopted adaptive current bias circuit into conventional class Ab CCII. The UIA consists of only two CCIIs and four resistors. Three instrumentation function of the UIA can be realized by selection of input signals and resistors. The simulation results show that the CCII has input impedance of 2.0$\Omega$ and the voltage gain of 60㏈ for frequency range from 0 to 50KHz when used as a voltage amplifier. The CCII has also good characteristics of current follower for current range from -100㎃ to ＋100㎃. The simulation results show that the UIA has three instrumentation amplifier functions without resistor matching. The UIA has the voltage gain of 40㏈ for frequency range from 0 to 100KHz when used as a fully-differential instrumentation amplifier. The power dissipations of the CCII and the UIA are 0.75㎽ and 1.5㎽ at supply voltage of $\pm$2.5V, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.77-84
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• 1998

A voltage controlled chaotic circuit has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated chaotic circuit consist of sample and hold circuits, op-amps, nonlinear function generator and two phase clock generator. The test results of the chaotic circuit show that periodic state, quasi-periodic state and chaotic state can be obtained according to the input control voltage with the ${\pm}$2.5V power supply and clock rate of 20kHz. In addition, two dimensional chaotic patterns have been observed by connecting this circuit in parallel or series

• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.38-45
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• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Journal of IKEEE
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• v.21 no.2
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• pp.154-157
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• 2017

This paper proposes the Low-Dropout regulator with two output. Each of the two output has feedback, and shared feedback loop. PMOS is added to solve the problem the occur when sharing the feedback loop. Thus eased the Load Transient Response. Also Using one of the bias citcuit and one of the pass transistor, Area is reduce by half compared to Existing Area that used to obtain output of two output.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.246-247
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• 2007

능동 구동형 유기 발광 소자 디스플레이용 수소화된 비정질 실리콘 박막 트랜지스터의 전류 안정성을 개선하기 위해, 음전압 인가방식을 채택한 새로운 화소 회로를 제안하였다. 제안한 회로는 5개의 트랜지스터를 사용하였고, 직전에 인가했던 $V_{GS}$에 따라 음의 전압을 인가하여 양의 전압에 의한 구동 박막 트랜지스터의 열화 현상을 줄여준다. 본회로는 SPICE 시뮬레이션을 통해 검증하였다.

• Journal of the Korea Society of Computer and Information
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• v.6 no.4
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• pp.125-130
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• 2001

The application of the operational trasconductance amplifier (OTA) in the design of a amplifier with voltage-controlled gam is demonstrated first. I designed OTA with linear operation and constructed a Amplifier with two OTA. In this design. I used OTA as open loop. Computer simulation result, designed OTA and Amplifier charateristics has a good matching with the theoritical value. The OTA is used often in open-loop and therefore it is wise to learn how to treat the two input pins independently, as a vertual short circuit can not be assured in many configurations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.1-7
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• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.41-46
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• 2012

A quadrature voltage controlled oscillator(QVCO) for X-band is presented in this paper. The QVCO has fabricated in Charted $0.13{\mu}m$ CMOS process. The QVCO consists of two cross-coupled differential VCO and two differential buffers. The QVCO is controlled by 4 bit of capacitor bank and control voltage of varactor. To have a linear quality factor of varactors, voltage biases of varactors are difference. The QVCO generates frequency tuning range from 6.591 GHz to 8.012 GHz. The phase noise is -101.04 dBc/Hz at 1MHz Offset when output frequency is 7.150 GHz. The supply voltage is 1.5 V and core current 6.5-8.5 mA.