• Applied Microscopy
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• v.25 no.2
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• pp.73-79
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• 1995

The oxidation of silicon wafers is an essential step in the fabrication of semiconductor devices. It is known to induce degradation of electrical properties and lattice strain of Si substrate from thermal oxidation process due to charged interface and thermal expansion mismatch from thermally grown SiO, film. In this study, convergent beam electron diffraction technique is employed to directly measure the lattice strains in Si(100) and $4^{\circ}$ - off Si(100) substrates with thermally grown oxide layer at $1200^{\circ}C$ for three hours. The ratios of {773}-{973}/{773}-{953} Higher Order Laue Zone lines were used at [012] zone axis orientation. Lattice parameters of the Si substrate as a function of distance from the interface were determined from the computer simulation of diffraction patterns. Correction value for the accelerating voltage was 0.2kV for the kinematic simulation of the [012]. HOLZ patterns. The change in the lattice strain profile before and after removal of oxide films revealed the magnitudes of intrinsic strain and thermal strain components. It was shown that $4^{\circ}$ -off Si(100) had much lower intrinsic strain as surface steps provide effective sinks for the free Si atoms produced during thermal oxidation. Thermal strain in the Si substrate was in compression very close to the interface and high concentration of Si interstitials appeared to modify the thermal expansion coefficient of Si.

• Journal of the Korean institute of surface engineering
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• v.48 no.5
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• pp.233-237
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• 2015

In order to investigate the potassium (K) gettering, Al-1%Si/$SiO_2$/PSG multilevel thin films were fabricated. Al-1%Si thin films and $SiO_2$/PSG passivations were deposited by using DC magnetron sputter techniques and APCVD (atmosphere pressure chemical vapor deposition), respectively. Heat treatment was carried out at $300^{\circ}C$ for 5 h in air. SIMS (secondary ion mass spectrometry) depth profiling analysis was used to determine the distribution of K, Al, Si, P, and other elements throughout the $SiO_2$/PSG passivated Al-1%Si thin film interconnections. Potassium peaks were observed throughout the $SiO_2$/PSG passivation layers, and especially the interface gettering at the $SiO_2$/PSG and at the Al-1%Si/$SiO_2$ interfaces was observed. Potassium gettering in Al-1%Si/$SiO_2$/PSG multilevel thin films is considered to be caused by a segregation type of gettering.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.25-29
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• 2008

Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

• Journal of Korea Foundry Society
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• v.13 no.6
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• pp.524-531
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• 1993

Dispersion behaviors of SiC particles and microstructures in Al-2%Si/SiCp composite prepared by Rheo-compocasting were studied with change of fabrication conditions(slurry temperature, agitation time) and additions of Mg($0{\sim}3wt.%$). Also, the microhardness change of matrix, interface and total in composites were examined with additions of Mg($0{\sim}3wt.%$). The dispersion of particles in the composites became relatively homogeneous with increase of Mg additions, agitation time and decrease of slurry temperature. Rate of occupied area by particle in matrix was increased as increase of Mg additions due to improvement of wettability between SiC particle and matrix. A favorable composites were obtained by melting under Ar atmospheric SiCp injection and bottom pouring system. According to the analysis of X-ray diffraction, $Mg_2Si$, $Al_4C_3$, $SiO_2$ and MgO, etc, intermetallic compounds were formed by chemical interreaction at interface of matrix and particles. The microhardness of interface is higher than that of matrix due to more strengthening of above intermetallic compounds. It was considered that the total hardness of the composites is improved by dispersing of SiCp and addition of Mg.

• Journal of the Korean institute of surface engineering
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• v.33 no.4
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.8-14
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• 2007

In this paper, $HfO_2$/Hf stacked film has been applied as the gate dielectric in MOS devices. The $HfO_2$ thin film was deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$ as precursors. Prior to the deposition of the $HfO_2$ film, a thin Hf metal layer was deposited as an intermediate layer. Round-type MOS capacitors have been fabricated on Si substrates with 2000${\AA}$-thick Al or Pt top electrode. The prepared film showed the stoichiometric components. At the $HfO_2$/Si interface, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. It seems that the intermediate Hf metal layer has a benefit for the enhancement of electric characteristics of gate dielectric in $HfO_2$/Si structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.468-473
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• 2003

In this paper, for enhancement of property on a-Si:H TFTs We measure interface characteristics of ferroelectrics thin film and a-Si:H thin film. First, SrTiO$_3$ thin film is deposited bye-beam evaporation. Deposited films are annealed for 1 hour in N2 ambient at $150^{\circ}C∼600^{\circ}C$. Dielectric characteristics of deposited SrTiO$_3$ films are very good because dielectric constant shows 50∼100 and breakdown electric field are 1 ∼ 1.5 MV/cm. a-SiN:H,a-Si:H(n-type a-Si:H) are deposited onto SrTiO$_3$ film to make MFNS(Meta1/ferroelectric/a-SiN:H/a-Si:H) by PECVD. After the C-V measurement for interface characteristics, MFNS structure shows no difference with MNS(Metal/a-SiN:H/a-Si:H) structure in C-V characteristics but the insulator capacitance value of MFNS structure is much higher than the MNS because of high dielectric constant of ferroelectric.

• Transactions on Electrical and Electronic Materials
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• v.9 no.1
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• pp.6-11
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• 2008

In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.465-465
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• 2013

Inorganic 물질인 SiO2 dielectric 위에 organic dielectric PVP (4-vinyphenol)를 spin coating으로 올려, inorganic/organic dielectric 형태의 double layer구조로 High-performance amorphous indiumgallium zinc oxide thin-film transistors (IGZO TFT)를 제작하여 보았다. SiO2 dielectric을 buffer layer로 80 nm, PVP는 10Wt% 400 nm로 구성하였으며, 200 nm single SiO2 dielectric과 동일한 수준의 leakage current 특성을 MIM Capacitor 구조를 통해서 확인할 수 있었다. 이 소자의 장점은 용액공정의 도입으로 공정 시간의 단축 및 원가 절감을 이룰 수 있으며, dielectric과 channel 사이의 균일한 interface의 형성으로 interface trap 개선 및 Yield 향상의 장점을 갖는다. 우리는 실험을 통해서 SiO2 buffer layer가 수직 electric field에 의한 leakage current을 제어하고, PVP dielectric은 interface를 개선하는 것을 확인하였다. Vth의 negative shift 및 slope의 향상으로 구동전압이 줄어들고, 균일한 I-V Curve 형성을 통해서 Process Yield의 향상을 확인하였다.

• Journal of the Korean Vacuum Society
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• v.22 no.3
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• pp.126-130
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• 2013

The sodium (Na) and moisture ($H_2O$) gettering phenomena were measured and analyzed in PSG/$SiO_2$ passivated Al-1%Si thin film interconnections. PSG/$SiO_2$ passivation and Al-1%Si thin films were deposited by using APCVD (atmosphere pressure chemical vapor deposition) and DC magnetron sputter techniques, respectively. SIMS (secondary ion mass spectrometry) depth profiling analysis was used to determine the distribution of sodium and moisture throughout the PSG/$SiO_2$ passivated Al-1%Si thin film interconnections. Both sodium and moisture peaks were observed strongly at the interfaces between layers rather than within the Al-1%Si thin film interconnections. Sodium peaks were observed at the interface between PSG and $SiO_2$ passivations, while moisture peaks were not observed.