• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.40-47
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• 2014

In this paper, $Al_2O_3$ film deposited by thermal atomic layer deposition (ALD) with diluted $NH_4OH$ instead of $H_2O$ was suggested for passivation layer and anti-reflection (AR) coating of the p-type crystalline Si (c-Si) solar cell application. It was confirmed that the deposition rate and refractive index of $Al_2O_3$ film was proportional to the $NH_4OH$ concentration. $Al_2O_3$ film deposited with 5 % $NH_4OH$ has the greatest negative fixed oxide charge density ($Q_f$), which can be explained by aluminum vacancies ($V_{Al}$) or oxygen interstitials ($O_i$) under O-rich condition. $Al_2O_3$ film deposited with $NH_4OH$ 5 % condition also shows lower interface trap density ($D_{it}$) distribution than those of other conditions. At $NH_4OH$ 5 % condition, moreover, $Al_2O_3$ film shows the highest excess carrier lifetime (${\tau}_{PCD}$) and the lowest surface recombination velocity ($S_{eff}$), which are linked with its passivation properties. The proposed $Al_2O_3$ film deposited with diluted $NH_4OH$ is very promising for passivation layer and AR coating of the p-type c-Si solar cell.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.303-303
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• 2012

X-선 반사율 측정법(XRR)은 비파괴적인 측정방법으로 수 nm의 두께를 정밀하게 측정할 수 있는 장점으로 반도체 산업현장에서 많은 관심과 연구가 이루어지고 있다. 이러한 XRR의 두께 측정 정밀도를 향상시키고 부정확한 결과를 방지하기 위하여 측정기기를 검증하고 보정할 수 있는 두께 표준물질을 필요로 하고 있다. 본 연구에서는 IBSD (ion beam sputtering deposition)와 ALD (atomic layer deposition)를 이용하여 5 nm, 10 nm의 $HfO_2$ 박막을 제작하고, XRR용 두께 표준물질로 응용할 수 있는지를 살펴보았다. 먼저 두께표준물질로 제작하기 위해서는 박막과 기판이 안정한 상태를 유지해야 한다. 이에 박막은 공기 중 노출에 의한 산화로 박막의 두께가 변할 수 있는 금속박막 대신에 공기 중에서도 안정한 산화물 박막인 $HfO_2$ 박막을 사용하고 기판은 Si wafer를 thermal공기 중에서도 안정한 산화물 박막인 $HfO_2$ 박막을 사용하고 기판은 Si wafer를 therma oxidation법을 이용하여 $1{\mu}m$ 두께로 제작한 비정질 $SiO_2$ 기판을 사용했다. 제작된 시료의 특성평가를 위해 XRR (X-ray reflectometer) 측정을 통해 두께, 거칠기 및 밀도를 확인하였고, TEM (transmission electron microscope)으로 두께 측정을 하여 XRR로 얻은 두께결과와 비교하였다. 측정결과를 확인하였을 때 두 증착 방법 중 ALD를 이용하여 제작한 시편에서는 박막과 기판사이의 interface가 sharp하여 반사율 곡선의 진폭이 크게 잘 나타났고 fitting 결과도 우수하여 IBSD로 증착한 시편보다 두께 표준물질로 응용하기에 더 적합하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.547-550
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• 2014

In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/$SiO_2$ structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatband voltage ($V_{FB}$) shift was positive. Near-interface trap charge density ($N_{it}$) and negative oxide trap charge density ($N_{ox}$) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitors is higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.

• Proceedings of the Materials Research Society of Korea Conference
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• 1994.05a
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• pp.165-166
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• 1994

The depth profiles of the as-grown and the annealed NH$_3$ oxide film in NH$_3$(7.5%)/$N_2$ ambient at 45$0^{\circ}C$ are analized . This annealing in the ambient of mixed gases removes the small quantities of N component from the NH$_3$ oxide film. In AES analysis, the NH$_3$ oxidation shows the exact stoichiometry of SiO$_2$ and a sharp slop at SiO$_2$/Si interface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.16-21
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• 2015

In this study, the effects of forming gas post metallization annealing (PMA) on recessed AlGaN/GaN-on-Si MOSHFET were investigated. The device employed an ICPCVD $SiO_2$ film as a gate oxide layer on which a Ni/Au gate was evaporated. The PMA process was carried out at $350^{\circ}C$ in forming gas ambient. It was found that the device instability was improved with significant reduction in interface trap density by forming gas PMA.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1122-1125
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• 2006

The TFT performances were enhanced and stabilized by plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of $Al_2O_3$ gate dielectric film. We attribute the improvement to the formation of a high quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics, and is regulated by the gap distance between the electrode and the polycrystalline Si surface.

• Journal of Sensor Science and Technology
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• v.20 no.4
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• pp.260-265
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• 2011

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.268-272
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• 2007

A fully integrable InP/InGaAs HPT with an ITO emitter contact was first fabricated by employing a $SiO_2$ passivation layer. The electrical and the optical characteristics of the HPT with a passivation layer were measured and compared with those of the HPT without a passivation layer. The only noticeable difference was the increased emitter series resistance of the HPT with a passivation layer. AES analysis was performed to explain the reason of the increased emitter series resistance. Results show that PECVD $SiO_2$ deposition and annealing processes cause the diffusion of oxygen to the interface and the depletion of tin at the interface, which may be responsible for the increase of the series resistance.