• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Korean Journal of Materials Research
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• v.11 no.2
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• pp.71-75
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• 2001

The reaction stability of nickel with side-wall materials of SiO$_2$ and Si$_3$N$_4$ on p-type 4"(100) Si substrate were investigated. Ni on 1300 $\AA$ thick SiO$_2$ and 500 $\AA$ - thick Si$_3$N$_4$ were deposited. Then the samples were annealed at 400, 500, 750 and 100$0^{\circ}C$ for 30min, and the residual Ni layer was removed by a wet process. The interface reaction stability was probed by AES depth Profiling. No reaction was observed at the Ni/SiO$_2$ and Ni/Si$_3$N$_4$, interfaces at 400 and 50$0^{\circ}C$. At 75$0^{\circ}C$, no reaction occurred at Ni/SiO$_2$ interface, while $NiO_x$ and Si$_3$N$_4$ interdiffused at Ni/Si$_3$N$_4$ interface. At 100$0^{\circ}C$, Ni layers on SiO$_2$ and Si$_3$N$_4$ oxidized into $NiO_x$ and then $NiO_x$ interacted with side-wall materials. Once $NiO_x$ was formed, it was not removed in wet etching process and easily diffused into sidewall materials, which could lead to bridge effect of gate-source/drain.

• Journal of the Korean Vacuum Society
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• v.12 no.S1
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• pp.63-66
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• 2003

It is experimentally shown that a $TiO_2$ film on Si(111) substrate was prepared by using the technique of D.C. reaction sputter deposition with $Ar^{+}$ ion beam bombardment, and a layer-like structure was observed from the depth profile of the interface between $TiO_2$ film and Si substrate with Scanning Electron Microscopy and Electron Probe. It was also surprisingly discovered that Ti atoms could be detected at about 9 $\mu$m depth. The $TiO_2$-Si interface bombarded by $Ar^{+}$ ion beams revealed multi-layer structures, a mechanism might be caused by defect diffusion, impurity and matrix relocation. Multi-relocations of impurity and matrix atoms were as a result of profile broadening of the $TiO_2$-Si interface, and the spread due to matrix relocation in this system is shown to exceed much more the spread due to impurity relocation.

• Korean Journal of Materials Research
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• v.12 no.2
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• pp.117-120
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• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.59-64
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• 1996

InSb MIS devices prepared by remote PECVD SiO$_{2}$ were fabricated. The SiO$_{2}$ films on InSb were deposited at atemperature range of 67~190$^{\circ}$C. The effects of deposition temperature on the structural characteristics of the SiO$_{2}$ films evaluated Auger electron spectroscopy showed that atomic raito of silicon to oxygen was 0.5 and composition toms were distributed uniformaly throuout the oxide film. The transition region is about 100$\AA$ for SiO$_{2}$/InSb interface. The leakage current density at 1MV/cm and the breakdownelectric field of the MiS device using SiO$_{2}$ film deposited at 105$^{\circ}$C were about 22 nA/cm$^{2}$ and 3.5MV/cm, respectively. The interface-state density at mid-bandgap extracted from 1 MHz high frequency C-V measurement was about 2X10$^{11}$ cm$^{-2}$eV$^{-1}$.

• Journal of the Korean Ceramic Society
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• v.28 no.8
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• pp.626-634
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• 1991

The specimens for the corrosion test were made by hot-pressing of SiC power with 2 wt% Nl2O3 and 10wt% Al2O3 additions at 200$0^{\circ}C$ and 205$0^{\circ}C$. The specimens were corroded in 37 mole% NaCl and 63 mole% Na2SO4 salt mixture at 100$0^{\circ}C$ up to 60 min. SiO2 layer was formed on SiC and then this oxide layer was dissolved by Na2O ion in the salt mixture. The rate of corrosion of the specimen containing 10 wt% Al2O3 was slower than that of the specimen containing 2 wt% Al2O3. This is due to the presence of continuous grain boundary phase in the specimen containing 10 wt% Al2O3. The oxidation of SiC produced gas bubbles at the SiC-SiO2 interface. The rate of corrosion follows a linear rate law up to 50 min. and then was accelerated. This acceleration is due to the disruption oxide layer by the gas evolution at SiC-SiO2 interface. Pitting corrosion has found at open pores and grain boundaries.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• Applied Chemistry for Engineering
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• v.9 no.7
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• pp.990-997
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• 1998

In this work, the $SiO_2$ films on the silicon substrate with different orientations were first prepared by the low temperature process using the ECR plasma diffusion as a function of microwave power and oxidation time. Before and after thermal treatment, the surface morphology, Si/O ratio from physicochemical properties, and the electrical properties of the oxide films were also investigated. The oxidation rate increased with microwave power, while surface morphology showed the nonuniform due to etching. The film quality, therefore, was lowered with increasing the defect by etching and the content of positive oxide ions in the oxide films from bulk by higher self-DC bias. The content of positive oxide ions in the oxide films with different Si orientations showed Si(100) < Si(111) < poly Si. The defects in $Si/SiO_2$ interface of $SiO_2$ film could be decreased by annealing, while $Q_{it}$ and $Q_f$ were independent of thermal treatment and the dependent on concentration of reactive oxide ions and self-DC bias of substrate. At microwave power of 300, and 400 W, the high quality $SiO_2$ film that had lower surface roughness and defect in $Si/SiO_2$ interface was obtained. The value of interface trap density, then, was ${\sim}9{\times}10^{10}cm^{-2}eV^{-1}$.

• ETRI Journal
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• v.19 no.1
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• pp.26-35
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• 1997

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using $Si_2H_6$ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer ($SiO_2$/Si), quartz and LPCVD-oxide, and annealed at 600$^{\circ}C$ in an $N_2$ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the $SiO_2$/Si starts from the interface between the a-Si and the substrate, so called interface-interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.