• 한국해양공학회지
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• 제16권6호
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• pp.60-64
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• 2002

This paper describes the machining characteristics of the MoSi$_2$--based composites through the process of electric discharge drilling with various tubular electrodes. In addition to hardness characteristics, microstructures of Nb/MoSi$_2$laminate composites were evaluated from the variation of fabricating conditions, such as preparation temperature, applied pressure, and pressure holding time. MoSi$_2$-based composites have been developed in new materials for jet engines of supersonic-speed airplanes and gas turbines for high-temperature generators. These high performance engines may require new hard materials with high strength and high temperature-resistance. Also, with the exception of grinding, traditional machining methods are not applicable to these new materials. Electric discharge machining (EDM) is a thermal process that utilizes a spark discharge to melt a conductive material. The tool electrode is almost -unloaded, because there is n direct contact between the tool electrode and the work piece. By combining a non-conducting ceramic with more conducting ceramic, it was possible to raise the electrical conductivity. From experimental results, it was found that the lamination from Nb sheet and MoSi$_2$ powder was an excellent strategy to improve hardness characteristics of monolithic MoSi$_2$. However, interfacial reaction products, like (Nb, Mo)SiO$_2$and Nb$_2$Si$_3$formed at the interface of Nb/MoSi$_2$, and increased with fabricating temperature. MoSi$_2$composites, with which a hole drilling was not possible through the conventional machining process, enhanced the capacity of ED-drilling by adding MbSi$_2$, relative to that of SiC or ZrO$_2$reinforcements.

• 한국전기전자재료학회논문지
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• 제18권11호
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• pp.996-1000
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide $(SiO_2)$ under both Negative-bias Temperature Instability (NBTI) and Hot-carrier-induced (HCI) stresses using P and NMOSFETS, The devices are annealed with hydrogen or deuterium gas at high-pressure $(1\~5\;atm.)$ to introduce higher concentration in the gate oxide. Both interface trap and oxide bulk trap are found to dominate the reliability of gate oxide during electrical stress. The degradation mechanism depends on the condition of electrical stress that could change the location of damage area in the gate oxide. It was found the trap generation in the gate oxide film is mainly related to the breakage of Si-H bonds in the interface or the bulk area. We suggest that deuterium bonds in $SiO_2$ film are effective in suppressing the generation of traps related to the energetic hot carriers.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권9호
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• pp.623-627
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• 1999

We report a new in-situ fluorine passivation method without in implantation by employing excimer laser annealing of $SiO_{x}F_{y}$/a-Si structure and its effects on p-channel poly-Si TFTs. The proposed method doesn't require any additional annealing step and is a low temperature process because fluorine passivation is simultaneous with excimer-laser-induced crystallization. A in-situ fluorine passivation by the proposed method was verified form XPS analysis and conductivity measurement. From experimental results, it has been shown that the proposed method is effective to improve the electrical characteristics, specially field-effect mobility, and the electrical stability of p-channel poly-Si TFTs. The improvement id due to fluorine passivation, which reduces the trap state density and forms the strong Si-F bonds in poly-Si channel and $SiO_2/poly-Si$ interface. From these results, the high performance poly-Si TFTs canbe obtained by employing the excimer-laser-induced fluorine passivation method.

• 한국재료학회지
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• 제8권12호
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• pp.1170-1175
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• 1998

하부전극 없이 MgO 중간층을 갖는 고농도로 도핑된 Si(100) 기판(MgO/Si)위에 고주파 마그네트론 스퍼터링 방법으로 as-deposited PZT 박막을 증착한후 $650^{\circ}C$ 온도에서 RTA 후속열처리를 실시하였다. 제작된 PZT 박막시료에 대해 MgO 중간층의 두께 및 후속열처리에 따른 결정학적, 전기적특성을 조사하였다. XRD 분석결과 MgO층이 전혀 증착되지 않은 bare Si 기판위에 증착된 PZT 시료는 pyrochlore 결정상만이 나타났으나 50 두께의 M gO층 위에 증착된 PZT/MgO/Si 박막시료는 전형적인 perovskite 결정구조를 나타내었다. SEM 및 AES 분석결과 PZT 박막두게는 약 7000 이었으며 비교적 매끄러운 계면형상을 보여 주었다. PZT 박막내의 각 성분원소가 깊이에 따라 비교적 균일한 분포를 나타내었다. $650^{\circ}C$의 온도로 후속열처리된 PZT/MgO/Si 박막의 1KHz 주파수에서 유전상수 ($\varepsilon_{r}$ )와 잔류분극 (2Pr)은 약 300 및 $14\mu$C/$\textrm{cm}^2$의 값을 각각 나타내었으며 누설전류의 크기는 약 $3.2\mu$A/$\textrm{cm}^2$이었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• 전자공학회논문지D
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• 제35D권12호
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• pp.68-74
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• 1998

본 논문에서는 electron cyclotron resonance (ECR) N₂O-플라즈마 산화막을 게이트 산화막으로 사용한 다결정 실리콘 박막 트랜지스터 (TFT)의 성능과 단채널 특성에 대하여 연구하였다. ECR NE₂O-플라즈마 게이트 산화막을 사용한 소자는 열산화막을 이용한 경우에 비해 우수한 성능과 억제된 단채널 효과를 나타낸다. 얇은 ECR N2O-플라즈마 산화막을 사용하여 n채널 TFT의 경우 3 ㎛, p채널 TFT의 경우 1㎛ 게이트 길이까지 문턱 전압 감소가 없는 소자를 얻었다. 이러한 특성 향상은 부드러운 계면, passivation 효과, 그리고 계면과 박막 내부에 존재하는 강한 Si ≡ N 결합 등에 기인한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.47-50
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• 2000

This paper investigated structural and electrical properties of $Y_2$ $O_3$ as a buffer layer of single transistor FRAM (ferroelectric RAM). $Y_2$ $O_3$ buffer layers were deposited at a low substrate temperature below 40$0^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post-annealing temperature, and suppression of interfacial $SiO_2$ layer generation. For a well-fabricated sample, we achieved that leakage current density ( $J_{leak}$) in the order of 10$^{-7}$ A/$\textrm{cm}^2$, breakdown electric field ( $E_{br}$ ) about 2 MV/cm for $Y_2$ $O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_2$ $O_3$/Si as low as 8.72x1010 c $m^{-2}$ e $V^{-1}$ . The low interface states were obtained from very low lattice mismatch less than 1.75%.

• 한국재료학회지
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• 제5권6호
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• pp.754-762
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• 1995

차세대 LSI용 유전체 박막으로서의 응용을 목적으로 RF 마그네트론 스퍼터링법으로 Si기판위에 SrTiO$_3$박막을 제조하였다. Ar과 $O_2$혼합가스 비, 바이어스 전압변화, 열처리 온도등의 증착조건을 다양하게 변화시키며 SrTiO$_3$박막을 제조하여 최적의 증착조건을 조사하였다. 박막의 결정성을 XRD로, 박막과 Si 사이의 계면의 조성분포를 AES로 각각 분석하였다. Ar과 $O_2$의 혼합가스를 스퍼터링 가스로 사용함으로써 결정성이 좋은 박막을 얻었다. 그리고 보다 치밀한 박막을 얻고자 바이어스 전압을 걸어주며 증착시켰다. 본 실험결과에서는 스퍼터링 가스는 Ar+20% $O_2$혼합가스, 바이어스 전압은 100V에서 좋은 결정성을 얻었다. 또한 하부전극으로 Pt, 완충층으로 Ti를 사용함으로써 SrTiO$_3$막과 Si 기판과의 계면에서 SiO$_2$층의 형성을 억제할 수 있었으며, Si의 확산을 막을 수 있었다. 전류 및 유전특성을 측정하기 위해 Au/SrTiO$_3$/Pt/Ti/SiO$_2$/Si로 구성된 다층구조의 시편을 제작하였다. Pt/Ti층은 RF 스퍼터링으로, Au 전극은 DC 마그네트론 스퍼터링법으로 증착시켰다 $600^{\circ}C$로 열처리함에 의해 미세하던 결정림들이 균일하게 성장하였으며, 이에 따라 유전율이 증가하고 누설전류가 감소하였다. $600^{\circ}C$에서 열처리한 두께 300nm의 막에서 유전율은 6.4fF/$\mu\textrm{m}$$^2$이고, 비유전상수는 217이었으며, 누설전류밀도는 2.0$\times$$10^{-8}$ A/$\textrm{cm}^2$로 양질의 SrTiO$_3$박막을 제조하였다.

• 한국세라믹학회지
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• 제42권2호
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• pp.104-109
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• 2005

PbO 완충층의 역할을 확인하기 위해, r.f. magnetron sputtering법을 이용하여 p-type (100) Si 기판 위에 $Pt/Pb_{1.1}Zr_{0.53}Ti_{0.47}O_{3}$와 PbO target으로 Pt/PZT/PbO/Si의 MFIS 구조를 제조하였다. MFIS 구조에 완충층으로 PbO를 삽입함으로써 PZT 박막의 결정성이 크게 향상되었고, 박막의 공정온도도 상당히 낮출 수 있었다. 그리고 XPS depth profile 분석 결과, PbO 증착시 기판온도가 PbO와 Si의 계면에서 Pb의 확산에 미치는 영향을 확인하였다. PbO 완충층을 삽입한 MFIS는 높은 메모리 윈도우와 낮은 누설전류 밀도를 가지는 추수한 전기적 특성을 나타내었다. 특히, 기판온도 $300^{\circ}C$에서 증착된 PbO를 삽입한 Pt/PZT(200nm, $400^{\circ}C)PbO(80nm)/Si$는 9V의 인가전압에서 2.OV의 가장 높은 메모리 윈도우 값을 나타내었다.