• 한국진공학회지
• /
• 제2권2호
• /
• pp.188-198
• /
• 1993

두께가 6~10 nm인 게이트 산화막의 계면에 염소(Cl)를 도입시킨 n-MOS capacitor 및 n-MOSFET을 제잘하여 물성적인 방법(SIMS, ESCA)과 전기적인 방법에 의해서 소자의 특성을 분석, 평가하였다. Last step TCA법을 이용하여 성장시킨 산화막은 No TCA법으로 성장시킨 것보다 mobility가 7% 정도 증가하였고, 결함 밀도도 감소하였다. Time-zero-dielectric-breakdown(TZDB)으로 측정한 결과, Cl를 도입한 막의 파괴 전계(breakdon field)는 18 MV/cm인데, 이것은 Cl을 도입하지 않은 것보다 약 0.6 MV/cm 정도 높은 값이다. 또한 time-dependent-dielectric-breakdown(TDDB) 결과로부터 수명이 20년 이상인 것으로 평가되었고, hot carrier 신뢰성 측정으로부터 평가한 소자의 수명도 양호한 것으로 나타났다. 이상의 결과에서 Cl을 계면에 도입시킨 게이트 산화막을 가진 소자가 좋은 특성을 나타내고 있으므로 Last step TCA법을 종래의 산화막 성장 방법 대신에 사용하면 MOSFET 소자의 새로운 게이트 절연막 성장법으로서 대단히 유용할 것으로 생각된다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.565-566
• /
• 2006

In this work, We study electrical characterization of $HfO_2$/Hf/Si films grown by Atomic Layer Deposition(ALD). Through AES(Auger Electron Spectroscopy), capacitance-voltage(C-V) and current-voltage(I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf metal layer in our structure effectively suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.8-9
• /
• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• E2M - 전기 전자와 첨단 소재
• /
• 제8권2호
• /
• pp.171-175
• /
• 1995

Optimum condition of remote plasma enhanced chemical vapor deposition using orthogonal array method was chosen. Characteristics of oxide films deposited by RPECVD with SiH$_{4}$ and N$_{2}$O gases were investigated. Etching rate of the optimized SiO$_{2}$ films in P-etchant was about 6[A/s] that was almost the same as that the high temperature thermal oxide. The films showed high dielectric breakdown field of more than 7[MV/cm] and a resistivity of 8*10$^{13}$ [.ohmcm] around at 7[MV/cm]. The interface trap density of SiO$_{2}$/Si interface around the midgap derived from the high frequency C-V curve was about 5*10$^{10}$ [/cm$^{2}$eV]. It was observed that the dielectric constant of the optimized SiO$_{2}$ film was 4.29.

• 마이크로전자및패키징학회지
• /
• 제23권2호
• /
• pp.49-55
• /
• 2016

차세대 반도체의 초미세 Cu 배선 확산방지층 적용을 위해 원자층증착법(atomic layer deposition, ALD) 공정을 이용하여 증착한 RuAlO 확산방지층과 Cu 박막 계면의 계면접착에너지를 정량적으로 측정하였고, 환경 신뢰성 평가를 수행하였다. 접합 직후 4점굽힘시험으로 평가된 계면접착에너지는 약 $7.60J/m^2$으로 측정되었다. $85^{\circ}C$/85% 상대습도의 고온고습조건에서 500시간이 지난 후 측정된 계면접착에너지는 $5.65J/m^2$로 감소하였으나, $200^{\circ}C$에서 500시간 동안 후속 열처리한 후에는 $24.05J/m^2$으로 계면접착에너지가 크게 증가한 것으로 평가되었다. 4점굽힘시험 후 박리된 계면은 접합 직후와 고온고습조건의 시편의 경우 RuAlO/$SiO_2$ 계면이었고, 500시간 후속 열처리 조건에서는 Cu/RuAlO 계면인 것으로 확인되었다. X-선 광전자 분광법 분석 결과, 고온고습조건에서는 흡습으로 인하여 강한 Al-O-Si 계면 결합이 부분적으로 분리되어 계면접착에너지가 약간 낮아진 반면, 적절한 후속 열처리 조건에서는 효과적인 산소의 계면 유입으로 인하여 강한 Al-O-Si 결합이 크게 증가하여 계면접착에너지도 크게 증가한 것으로 판단된다. 따라서, ALD Ru 확산방지층에 비해 ALD RuAlO 확산방지층은 동시에 Cu 씨앗층 역할을 하면서도 전기적 및 기계적 신뢰성이 우수할 것으로 판단된다.

• 한국진공학회지
• /
• 제5권3호
• /
• pp.223-228
• /
• 1996

$SiO_2$ insulator layers on InSb have been prepared by remote PECVD system a low temperature below $200^{\circ}C$. The effects of deposition pressure, temperature, and gas flow ratio on the physical and electrical characteristics of the $SiO_2$ were studied. The InSb MIS device using $SiO_2$ was fabricated and measured its current-voltage and capacitance-voltage characteritance-voltage charateristics at 77K. The films evaluated Auger electron spectroscopy showed that composition atoms were distributed uniformaly throughout the oxide film and the outdiffusion of substrate atoms into the oxide were few. The leakage current density of the MIS device was about 6.26nA/$\textrm{cm}^2$ at 0.75MV/cm , and the breakdown voltage was about 1MV/cm. The interface-stage density at mid-bandgap extracted from 1MHz C-V measurement was $54\times 10^{11}\textrm{cm}^2-2V^{-1}$.

• 한국전기전자재료학회논문지
• /
• 제25권1호
• /
• pp.24-28
• /
• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

• 전자공학회논문지A
• /
• 제33A권6호
• /
• pp.151-157
• /
• 1996

We propose a mechanism for the formation of pinholes in the Si-buffer layer, through the observations with varying the process- and structure variables in the SEPOX (selective poly-oxidation) process, an isolation method for sub-u DRAMs. Pinholes are formed through the accumulation of Si vacancies generated by the oxidation of Si, in which Si atoms leave the sites (vacancies) at the Si/SiO$_{2}$ interfaces and diffuse into the oxide to be oxidized near interface. In the course of the accumulation of Si-vacancies, the stress induced in the Si-buffer layer affects the migration of vacancies to result in the final size and distribution of pinholes. This paper may be, to our knowledge, the first report about the oxidation-induced pinhole in the Si/SiO$_{2}$ system.

• Transactions on Electrical and Electronic Materials
• /
• 제15권2호
• /
• pp.73-76
• /
• 2014

$Pt/Al_2O_3/La_2Si_5O_x/SiO_2/Si$ charge trap memory capacitors were prepared, in which the $La_2Si_5O_x$ film was used as the charge trapping layer, and the effects of post annealing atmospheres ($NH_3$ and $N_2$) on their memory characteristics were investigated. $La_2O_3$ nanocrystallites, as the storage nodes, precipitated from the amorphous $La_2Si_5O_x$ film during rapid thermal annealing. The $NH_3$ annealed memory capacitor showed higher charge storage performances than either the capacitor without annealing or the capacitor annealed in $N_2$. The memory characteristics were enhanced because more nitrogen was incorporated at the $La_2Si_5O_x/SiO_2$ interface and interfacial reaction was suppressed after the $NH_3$ annealing treatment.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
• /
• pp.357-358
• /
• 2007

Raman spectra of poly (polycrystalline) 3C-SiC thin films, which were deposited on the oxidized Si substrate by APCVD, have been measured. They were used to study the mechanical characteristics of poly 3C-SiC grown in various temperatures. TO and LO modes of 2.0 m poly 3C-SiC grown at 1180 C occurred at 794.4 and $965.7\;cm^{-1}$. Their FWHMs (full width half maximum) were used to investigate the stress and the disorder of 3C-SiC. The broad FWHM can explain that the crystallinity of 3C-SiC grown at 1180 C becomes poly crystalline instead of the disordered crystal. The ratio of intensity $I_{(LO)}/I_{(TO)}$ 1.0 means that the crystal defect of 3C-SiC/$SiO_2$/Si is small. The biaxial stress of poly 3C-SiC was obtained as 428 MPa. In the interface of 3C-SiC/$SiO_2$, the phonon mode of C-O bonding appeared at $1122.6\;cm^{-1}$. The phonon modes related to D and G bands of C-C bonding were measured at 1355.8 and $1596.8\;cm^{-1}$ respectively.