• Title/Summary/Keyword: $0.18{\mu}m$ Technology

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An Unrecorded Species of Pratylenchus Ioosi Loof (Tylenchida: Pratylenchidae) from Tea in Korea (한국산기종 차나무뿌리썩이선충, Pratylenchus Ioosi Loof(참선충 목: 뿌리썩이선충科))

  • Park, Byeong-Yong;Park, Dong-Ro;Lee, Jae-Kook;Park, Young-Eoun;Shin, Gil-Ho
    • Korean journal of applied entomology
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    • v.41 no.4
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    • pp.299-303
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    • 2002
  • Pratylenchus loosi Loof, 1960 is recorded for the first time from Korea. The nematode was isolated from the roots of tea (Thea sinensis L.) and soil around the roots from Yeongam-gun, Jeo-llanam-do and Namjeju-gun, Jeju-do, Korea. This species has two lip annuli. The female is 433-646 $\mu\textrm{m}$ long: a= 29.1-37.5, b = 5.1-6.4, c = 15.0-21.3, vulva(%) = 73.0-85.4. The male body length is 408-512$\mu\textrm{m}$ long: a=36.1-40.0, b=4.8-6.7, c =17.0-19.0, and spicule = 14.1-18.0 $\mu\textrm{m}$. The stylet is 11.6-18.0 $\mu\textrm{m}$ long and the number of incisures is four. The shape of spermatheca filled with sperm is broadly rounded, oval and quadrangular The shape of tail is narrowly round to subacute.

Implementation of Ternary Valued Adder and Multiplier Using Current Mode CMOS (전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현)

  • Seong, Hyeon-Kyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.9
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    • pp.1837-1844
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    • 2009
  • In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.

Fabrication of Schottky diodes for RFID tag integration using Standard $0.18{\mu}m$ CMOS process (RFID tag 집적화를 위한 $0.18{\mu}m$ 표준 CMOS 공정을 이용한 쇼트키 다이오드의 제작)

  • Shim, Dong-Sik;Min, Young-hun
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.591-592
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    • 2006
  • Schottky diodes for Radio-frequency identification (RFID) tag integration on chip were designed and fabricated using Samsung electronics System LSI standard $0.18{\mu}m$ CMOS process. Schottky diodes were designed as interdigitated fingers array by CMOS layout design rule. 64 types of Schottky diode were designed and fabricated with the variation of finger width, length and numbers with a $0.6{\mu}m$ guard ring enclosing n-well. Titanium was used as Schottky contact metal to lower the Schottky barrier height. Barrier height of the fabricated Schottky diode was 0.57eV. DC current - voltage measurements showed that the fabricated Schottky diode had a good rectifying properties with a breakdown voltage of -9.15 V and a threshold voltage of 0.25 V.

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Simultaneous determination of sunscreen agents in cosmetics by HPLC (HPLC를 이용한 화장품 중의 자외선 차단제 동시분석방법 연구)

  • Lee, Yong-Hwa;Yang, Jae-Chan
    • Journal of the Korean Applied Science and Technology
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    • v.29 no.4
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    • pp.577-584
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    • 2012
  • The simultaneous analysis of sun screen agents in commercial cosmetic samples was carried out by High Perfomance Liquid Chromatography(HPLC). The cosmetic samples are directly dissolved in Tetrahydrofurane(THF) and filtered using $0.45{\mu}m$ filter. The water/methanol/THF was used for the mobile phase of gradient conditions. An Extend C18 reversed-phase column and the selected UV/Visible detector was applied. The analysis results of HPLC showed good linearity with correlation coefficient of $r^2$=0.9992 in the rage of $50{\sim}800{\mu}g/mL$ and detection limit of $0.01{\mu}g/mL$.

Simultaneous determination of parabens in cosmetics by LC/MS (LC/MS를 이용한 화장품 중의 parabens 동시 분석 방법 연구)

  • Park, Gyo-Beom;Lee, Sueg-Geun
    • Analytical Science and Technology
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    • v.23 no.1
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    • pp.54-59
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    • 2010
  • The simultaneous analysis of parabens in cosmetic samples was carried out by LC/MS. The cosmetic samples are directly dissolved in methanol and filterated using $0.45\;{\mu}m$ filter. The methanol-water was used for the mobile phase of gradient conditions. An Extend $C_{18}$ reverse-phase column and the selected ion monitoring (SIM) mode were applied. The analysis results of LC/MS showed good linearity with correlation coefficient of $r^2$=0.9993 in the range of 0.05 to $10\;{\mu}g$/mL and detection limit of $0.01\;{\mu}g$/mL.

Effects of Leveler on the Trench Filling during Damascene Copper Plating (전해전착시 상감 구리 배선의 충전에 미치는 레벨러의 효과)

  • Lee, Yu-Young;Park, Young-Joon;Lee, Jae-Bong;Cho, Byung-Won
    • Journal of the Korean Electrochemical Society
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    • v.5 no.3
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    • pp.153-158
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    • 2002
  • The effects of leveler on the copper trench filling were investigated during damascene plating process. To investigate the trench filling effect with the addition of a leveler, a cross-section images of the electroplated trenches with the width of$0.37{\mu}m,\;and\;0.18{\mu}m$ were observed by field emission scanning electron microscope (FE-SEM). Polyethylene glycol(PEG), 3-mercapto-1-propanesulfonic acid and Janus Green B were used as a carrier, an accelerator and a leveler. $0.37{\mu}m$ trenches were superfilled without voids, but there was voids formation in $0.18{\mu}m$ trenches when the leveler was not added into the electrolyte. On the other hand $0.18{\mu}m$ trenches were superfilled without voids with the addition of the leveler due to the reduction growth rate of copper at protrusions and edges, which yield smooth final deposit surface. The leverer effect becomes more significant as the width of trenches becomes smaller when trenches are filed.

Mass Size Distribution of Atmospheric Aerosol Particles with Nanosampler Cascade Impactor in Jinju City (다단 임팩터 Nanosampler를 이용한 진주시 대기에어로졸입자의 입경별 질량농도 특성)

  • Park, Jeong-Ho;Jang, Min-Jae;Kim, Hyoung-Kab
    • Journal of Environmental Science International
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    • v.24 no.5
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    • pp.679-687
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    • 2015
  • Atmospheric aerosol particles were investigated at GNTECH university in Jinju city. Samples were collected using the Nanosampler period from January to December 2014. The Nanosampler is a 6 stage cascade impactor(1 stage : > $10{\mu}m$, 2 stage : $2.5{\sim}10{\mu}m$, 3 stage : $1.0{\sim}2.5{\mu}m$, 4 stage : $0.5{\sim}10{\mu}m$, 5 stage : $0.1{\sim}0.5{\mu}m$, back-up : < $0.1{\mu}m$) with the stages having 50% cut-off ranging from 0.1 to $10{\mu}m$ in aerodynamic diameter. The mass size distribution of Atmospheric aerosol particles was unimodal with peak at $1.0{\sim}2.5{\mu}m$ or $0.5{\sim}1.0{\mu}m$. The annual average concentrations of TSP, $PM_{10}$, $PM_{2.5}$, $PM_1$, $PM_{0.5}$ and $PM_{0.1}$ were $44.0{\mu}g/m^3$, $40.3{\mu}g/m^3$, $31.4{\mu}g/m^3$, $18.0{\mu}g/m^3$, $8.0{\mu}g/m^3$, $3.0{\mu}g/m^3$, respectively. On average $PM_{10}$, $PM_{2.5}$, $PM_1$, $PM_{0.5}$ and $PM_{0.1}$ make up 0.91, 0.70, 0.41, 0.19 and 0.07 of TSP, respectively. The annual average of $PM_{2.5}/PM_{10}$ ratio was 0.77.

Quantitative Analysis of trans-Resveratrol in Red Wines by Solid Phase Extraction and LC/MS (고체상 추출법과 LC/MS를 이용한 적포도주 중의 trans-Resveratrol 분석)

  • Park, Gyo-Beom;Moon, Hyoung-Sil;Lee, Sueg-Geun
    • Analytical Science and Technology
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    • v.16 no.2
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    • pp.125-133
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    • 2003
  • In order to determine the contents of trans-resveratrol in red wine, which was mainly consumed in Korea, both LC/MS-ESI and LC/MS-APCI methods were used after solid-phase (Sep-Pak $C_{18}$-cartridges) extraction. The contents of trans-resveratrol obtained by LC/MS-ESI were detected in the range of $0.06-4.31{\mu}g/mL$. The recoveries were ranged from 88.4 to 97.9%. The values of relative standard deviation were ranged from 0.6 to 4.6% and the detection limit was $0.001{\mu}g/mL$. The contents of trans-resveratrol obtained by LC/MS-APCI were detected in the range of $0.09-4.02{\mu}g/mL$ and the detection limit was $0.005{\mu}g/mL$.

A Novel Electrostatic Discharge (ESD) Protection Device by Current Feedback Using $0.18\;{\mu}m$ Process ($0.18\;{\mu}m$ 공정에서 전류 피드백을 이용한 새로운 구조의 정전기 보호 소자에 관한 연구)

  • Bae, Young-Seok;Lee, Jae-In;Jung, Eun-Sik;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.3-4
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    • 2009
  • As device process technology advances, effective channel length, the thickness of gate oxide, and supply voltage decreases. This paper describes a novel electrostatic discharge (ESD) protection device which has current feedback for high ESD immunity. A conventional Gate-Grounded NMOS (GGNMOS) transistor has only one ESD current path, which makes, the core circuit be in the safe region, so an GGNMOS transistor has low current immunity compared with our device which has current feedback path. To simulate our device, we use conventional $0.18\;{\mu}m$ technology parameters with a gate oxide thickness of $43\;{\AA}$ and power supply voltage of 1.8 V. Our simulation results indicate that the area of our ESD protection, device can be smaller than a GGNMOS transistor, and ESD immunity is better than a GGNMOS transistor.

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Ka-band Power Amplifiers for Short-range Wireless Communication in $0.18-{\mu}m$ CMOS Process ($0.18-{\mu}m$ CMOS공정을 이용한 Ka 대역 근거리 무선통신용 전력증폭기 설계)

  • He, Sang-Moo;Lee, Jong-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.131-136
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    • 2008
  • Two Ka-band 3-stage power amplifiers were designed and fabricated using $0.18-{\mu}m$ CMOS technology. For low loss matching networks for the amplifiers, two substrate-shielded transmission line structures, having good modeling accuracy up to 40 GHz were used. The measured insertion loss of substrate-shielded microstrip-line (MSL) was 0.5 dB/mm at 27 GHz. A 3-stage CMOS amplifier using substrate-shielded MSL achieved a 14.7-dB small-signal gain and a 14.5-dBm output power at 27 GHz in a compact chip area of 0.83$mm^2$. The measured insertion loss of substrate-shielded coplanar waveguide (CPW) was 1.0 dB/mm at 27 GHz. A 3-stage amplifier using substrate-shielded CPW achieved a 12-dB small-signal gai and a 12.5-dBm output power at 26.5 GHz. This results shows a potential of CMOS technology for low cost short-range wireless communication components and system.