• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• Journal of IKEEE
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• v.20 no.3
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• pp.318-321
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• 2016

As IoT industry are growing fast, The importance of power management system is also being magnified. CMOS High power-supply rejection ratio(PSRR) Low-dropout(LDO) regulator is achieved by the proposed ripple Subtractor, Feed-forward capacitor and OTA in this paper. The LDO is implemented in $0.18-{\mu}m$ CMOS technology. With the proposed structures, in the maximum loading of 40mA, Simulation result achieves PSRR of -73.4dB at 500kHz and PSRR better than -40dB when frequency is below 10MHz with $6.8-{\mu}F$ output capacitor.

• Journal of Navigation and Port Research
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• v.36 no.9
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• pp.737-740
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• 2012

A miniaturized CMOS bandpass filter for a single RF transceiver system is presented, using diagonally end-shorted coupled lines and lumped capacitors. In contrast to conventional miniaturized coupled line filters, it is proven that the effective permittivity variation of the coupled transmission line has no effect on shifting the center frequency when the bandpass filter is highly miniaturized. A bandpass filter at a center frequency of 2 GHz was fabricated by $0.18{\mu}m$ CMOS technology. The insertion loss with the die area of $1500{\mu}m{\times}1000{\mu}m$ is -5.14 dB. Simulated results are well agreed with the easurements. It also verify the center frequency stability in the compact size bandpass filter.

• The Journal of the Korea Contents Association
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• v.13 no.10
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• pp.54-61
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• 2013

This paper presents a simplified hardware based edge detection circuit which is based on an analog correlator combining with the neighbor pixels in CMOS image sensor. A pixel element of the edge detector consists of an active pixel sensor and an analog correlator circuit which connects two neighbor pixels. The edge detector shares a comparator on each column that the comparator decides an edge of the target pixel with an adjustable reference voltage. The circuit detects image edge from CIS directly that reduces area and power consumption 4 times and 20%, respectively, compared with the previous works. And also it has advantage to regulate sensitivity of the edge detection because the threshold value is able to control externally. The fabricated chip has 34% of fill factor and 0.9 ${\mu}W$ of power per a pixel under 0.18 ${\mu}m$ CMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.140-144
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• 2004

The selectable dual band LNA usually uses common source transistor pair each input of which is selectively driven at a different frequency in a series resonant form. This paper analyzes the degradation in noise figures of the MOSFET common source pair with series resonance when it is driven concurrently at both inputs with different frequencies as a concurrent dual band LNA. Results of analysis will be compared with the measured noise figures of CMOS LNA with double inputs fabricated in 0.18 $\mu\textrm{m}$ CMOS process. Additionally, analyzing the contributions of FET channel noise and source noise from the LNA operating in the other band, this paper proposes optimum matching topology which minimizes the added noises for concurrent operation.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.419-420
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• 2008

A power amplifier(PA) has been designed for 900 MHz-band applications. The PA consists of a single-ended CMOS amplifier which has $0.18{\mu}m{\times}64{\times}6$ gate width. The PA has been designed using $0.18{\mu}m$ CMOS process. At 900 MHz, the PA exhibit an output power of 20.8 dBm and a power-added efficiency(PAE) of 58.4 % with 22.2 dB power gain.

• ETRI Journal
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• v.33 no.3
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• pp.462-465
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• 2011

A millimeter-wave (mm-wave) high-linear low-noise amplifier (LNA) is presented using a 0.18 ${\mu}m$ standard CMOS process. To improve the linearity of mm-wave LNAs, we adopted the multiple-gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate-source bias at the last stage of LNAs, third-order input intercept point (IIP3) and 1-dB gain compression point ($P_{1dB}$) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2457-2464
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• 2011

In this paper, a vibration energy harvesting circuit using a piezoelectric device is designed. MPPT(Maximum Power Point Tracking) control function is implemented using the electric power-voltage characteristic of a piezoelectric device to deliver the maximum power to load. The designed MPPT control circuit traces the maximum power point by periodically sampling the open circuit voltage of a full-wave rectifier circuit connected to the piezoelectric device output and delivers the maximum available power to load. The proposed vibration energy harvesting circuit is designed with $0.18{\mu}m$ CMOS process. Simulation results show that the maximum power efficiency of the designed circuit is 91%, and the chip area except pads is $700{\mu}m{\times}730{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.