• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2023-2026
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• 2002

This paper explains the study of controller design applied to SRM(Switched Reluctance Motor) concept. This controller executes controller algorithms via ${\mu}$-processor to increase stability and precise measurement, and VHDL (Very high speed integrated circuit Hardware Description Language) is designed to generate SRM driving signal. During initial period, SRM controller was designed to control .respective target RPM (Revolution per minutes) and PR (Proportional Integral Differential) coming from the PC(Personal Computer) monitor program, and receiving clockwise and counter-clockwise rotation signal and target RPM coming from the front panel, and receiving the location of rotational element and RPM generating from the position censor during activation period.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.1
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• pp.78-86
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• 1995

$H_{\infty}$ Controller of seeker scan-loop is designed using LSDP proposed by McFarlane. The performance and robustness of $H_{\infty}$ controller are analyzed using robustness theorems by Lehtomaki and compared with those of the LQG/LTR controller. Especially, structured singular value .mu. -test of Doyle is used to evaluate robust performance of seeker scan-loop. It is demonstated that seeker scan-loop by $H_{\infty}$ controller is very robust to model uncertainties described by additive and multiplicative perturbations.

• Journal of Advanced Marine Engineering and Technology
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• v.35 no.6
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• pp.820-828
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• 2011

Energy saving is one of the most important factors for profits in marine transportation. In order to reduce the specific fuel oil consumption, the ship's propulsion efficiency must be increased as much as possible. The propulsion efficiency depends upon a combination of propulsion engine and propeller that has better efficiency as lower rotational speed. As the engine has lower speed the variation of rotational torque become larger because of the longer delay time in fuel oil injection process. In this study, robust control theory is applied to the design of engine speed controllers which are sub-optimal $H_{\infty}$ controller, $H_{\infty}$ loop-shaping controller and ${\mu}$-synthesis controller considering robust stability and robust performance. And the validity of these three controllers is investigated through the results of computer simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.26-34
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• 1999

According to increase of nonlinear power electronics equipment, active power filters have been researched and developed for many years to compensate harmonic disturbances and reactive power. However the commercial of active power filter is being proceeded slowly, because the cost of active power filter compared to the passive filter for harmonic and reactive power compensation is expensive. Especially, the use of DSP (Digital Signal Processing) chip, which is frequently used to control 3-phase active power filter, is a factor of increasing the cost of active power filters. On the other hand, the use of only analog controller makes the controller's circuits much more complicate and depreciates the flexibilities of controller. In this paper, a controller with low cost for 5[kVA] 3-phase active power filter system is designed. To reduce the expense of active filter system, the presented controller is composed of digital control part using Intel 80C196KC $\mu$P and analog control part using hysteresis controller for current control. Characteristic analysis of designed controller for active filter system is performed by computer simulation and compensating characteristics of the designed controller are verified by experiment.tegy can apply to the vector control, leading to better output torque capability in the ac motor drive system. This strategy is that in the overmodulation range, the d-axis output current is given a priority to regulate the flux well, instead the q-axis output curent is sacrificed. Therefore, the vector control even in the overmodulation PWM operation can be achieved well. For this purpose, the d-axis output voltage of a current controller to control the flux is conserved. the q-axis output voltage to control the torque is controlled to place the reference voltage vector on the hexagon boundary in case of the overmodulation. The validity of the proposed overall scheme is confirmed by simulation and experiments for a 22[kW] induction motor drive system.

• Proceedings of the SAREK Conference
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• 2008.06a
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• pp.1105-1110
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• 2008

An experimental study was performed to control Ice Packing Factor (IPF) of ice slurry in a pipe in a real time. This paper presented the concept that IPF can be adjusted by the amount of the solution contained to ice slurry. Based on this concept, we designed IPF controller consisting of the outlet tube providing ice slurry and the upper tube discharging only a solution through holes, and investigated the technical validity and efficiency of the controller experimentally. As a result, the original proposed IPF controller could not control IPF of ice slurry in a pipe. This is because an ice of ice slurry was drained out into not only the outlet but also the upper of the controller due to the size of the holes relatively large compared to the ice particle. Therefore, we changed the hole size of IPF controller surface using fine meshes and then, observed that IPF in a pipe was increased by $4{\sim}7$ percent when the hole size was $80{\mu}m$ and less.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.209-212
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• 2000

This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX＋Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.325-328
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• 2003

This paper is studied about the DC motor synchronization control for robot driving DC motor where is located in long distance place. The DC motors are received the speed order through internet with realtime. We designed the PID controller that related to PWM voltage and revolution given by 80C196KC $\mu$-Processor to move DC motors, so two motors were synchronized quickly about the order of random speed or location by PID controller. Furthermore, we controlled motors with realtime through internet by using lava platform that had a excellent compatibility, and monitored the speed of two motors.

• Journal of IKEEE
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• v.19 no.2
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• pp.210-218
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• 2015

In this paper an auto-switching energy harvesting circuit using vibration and thermoelectric energy is proposed. Since the maximum power point of a thermoelectric generator(TEG) output and a vibration device(PEG) output is 1/2 of their open-circuit voltage, an identical MPPT controller can be used for both energy sources. The proposed circuit monitors the outputs of the TEG and PEG, and chooses the energy source generating a higher output voltage using an auto-switching controller, and then harvests the maximum power from the selected device using the MPPT controller. The proposed circuit is designed in a $0.35{\mu}m$ CMOS process and its functionality has been verified through extensive simulations. The designed chip occupies $1.4mm{\times}1.2mm$ including pads.