• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Korean Journal of Optics and Photonics
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• v.14 no.1
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• pp.38-43
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• 2003

Fabrication process of strain-induced channel waveguides in $LiNbO_3$ was developed using strain-optic effect and compressional strain due to ~1.4 $\mu\textrm{m}$ surface Mo/Pt metal film. Characterization of the channel waveguides revealed a single transverse and depth mode in both TE and TM polarizations. Measurements showed total insertion loss of 6.2 and 7.7 ㏈/cm for TM and TE polarizations. respectively. Electro-optic intensity modulators with 11 mm long electrode length and 21 $\mu\textrm{m}$ electrode gap at $\lambda$ = 1.15 ${\mu}{\textrm}{m}$have been produced in $LiNbO_3$ substrates using strain-induced channel waveguides. Modulation depth of 100% at $\pi$-radian voltage of 16.1V has been demonstrated. Also, 1$\times$2 on/off power splitters at $\lambda$ = 0.63 $\mu\textrm{m}$ have been produced using strain-induced channel waveguides. On/off voltage of $\pm$ 25V has been demonstrated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• The Korean Journal of Physiology
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• v.29 no.2
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• pp.225-232
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• 1995

The present study was conducted to evaluate the effect of phorbol 12,13-dibutyrate (PDBu) on the contraction of rabbit jugular vein in vitro. PDBu concentrations of greater than 10 nM induced a periodic contraction which was composed of rapid contraction, plateau and slow relaxation. The frequency of periodic contraction increased as PDBu concentration increased. The PDBu-induced contraction was inhibited by staurosporine (100 nM), it was not changed by tetrodotoxin $(1\;{\mu}M).$ In $Ca^{2+}$-free medium, PDBu induced a sustaining contraction, but not periodic contraction. Addition of $Ca^{2+}$ to medium evoked periodic contraction which was inhibited by nifedipine, PDBu concentrations of greater than $0.1\;{\mu}M$ increased ^{45}Ca^{2+}$ uptake without changing $^{45}Ca^{2+}$ efflux. Charybdotoxin and apamin, $Ca^{2+}$-activated K^{+}$ channel blockers, did not affect the PDBu-induced periodic contraction, whereas tetraethylammonium (TEA) abolished the periodicity. Pinacidil $(10\;{\mu}M).$, a potassium channel activator, blocked PDBu induced periodic contraction, which was recovered by glybenclamide $(10\;{\mu}M).$. In high potassium solution, PDBu did not produce the periodic contraction. These results suggest that the PDBu-induced periodicity of contraction is modulated by voltage dependent $Ca^{2+}$ channel and ATP-sensitive $K^{+}$ channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• The Korean Journal of Physiology and Pharmacology
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• v.20 no.1
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• pp.119-127
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• 2016

Dihydropyridine (DHP) calcium channel blockers (CCBs) have been widely used to treat of several cardiovascular diseases. An excessive shortening of action potential duration (APD) due to the reduction of $Ca^{2+}$ channel current ($I_{Ca}$) might increase the risk of arrhythmia. In this study we investigated the electrophysiological effects of nicardipine (NIC), isradipine (ISR), and amlodipine (AML) on the cardiac APD in rabbit Purkinje fibers, voltage-gated $K^+$ channel currents ($I_{Kr}$, $I_{Ks}$) and voltage-gated $Na^+$ channel current ($I_{Na}$). The concentration-dependent inhibition of $Ca^{2+}$ channel currents ($I_{Ca}$) was examined in rat cardiomyocytes; these CCBs have similar potency on $I_{Ca}$ channel blocking with $IC_{50}$ (the half-maximum inhibiting concentration) values of 0.142, 0.229, and 0.227 nM on NIC, ISR, and AML, respectively. However, ISR shortened both $APD_{50}$ and $APD_{90}$ already at $1{\mu}M$ whereas NIC and AML shortened $APD_{50}$ but not $APD_{90}$ up to $30{\mu}M$. According to ion channel studies, NIC and AML concentration-dependently inhibited $I_{Kr}$ and $I_{Ks}$ while ISR had only partial inhibitory effects (<50% at $30{\mu}M$). Inhibition of $I_{Na}$ was similarly observed in the three CCBs. Since the $I_{Kr}$ and $I_{Ks}$ mainly contribute to cardiac repolarization, their inhibition by NIC and AML could compensate for the AP shortening effects due to the block of $I_{Ca}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.728-731
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• 2009

We report numerical simulations to investigate of the dependendce of the on/off current ratio and channel charge distributions in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width and thicknesses. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L of $10\;{\mu}m$, but varying the channel width W from 5 nm to $5\;{\mu}m$, and thickness t from 10 nm to 30 nm. We have show that $Q_{ON}/Q_{OFF}$ drastically decreases (from $^{\sim}2.9{\times}10^4$ to $^{\sim}9.8{\times}10^3$) as the channel thickness increases (from 10 nm to 30 nm). As a result of the simulation using a quantum model, even higher charge density in the bottom of SiNW channel was observed then in the bottom of control channel.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.7
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• pp.6-12
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• 2009

In this paper, we propose the opportunistic channel state information feedback scheme for eigen based scheduling in multiuser MIMO systems. According to 3GPP SMC channel model, the system capacity of MU-MIMO systems is severly degraded, since the antennas are highly correlated in urban macro cell. Although the eigen based scheduling scheme mitigates the adverse effect of the antenna correlation, it achieves only small amount of the multiuser diversity gain. Since the opportunistic channel state information scheme can achieve sufficient multiuser diversity gain, the system capacity of MU-MIMO systems can be improved. The system capacity improvement is verified by the computer simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.561-567
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• 2017

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.33-33
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• 2009

Silicon nano-structures have great potential in bionic sensor applications. Atomic force microscopy (AFM) anodic oxidation have many advantages for the nanostructure fabrication, such as simple process in atmosphere at room temperature, compatibility with conventional Si process. In this work, we fabricated simple FET structures with channel width W~ 10nm (nanowire) and $1{\mu}m$ (nano-ribbon) on ~10, 20 and 100nm-thinned silicon-on-insulator (SOI) wafers in order to investigate the surface effect on the transport characteristics of nano-channel. For further quantitative analysis, we carried out the 2D numerical simulations to investigate the effect of channel surface states on the carrier distribution behavior inside the channel. The simulated 2D cross-sectional structures of fabricated devices had channel heights of H ~ 10, 20, and 100nm, widths of L ~ $1{\mu}m$ and 10nm respectively, where we simultaneously varied the channel surface charge density from $1{\times}10^{-9}$ to $1{\times}10^{-7}C/cm2$. It has been shown that the side-wall charge of nanowire channel mainly affect the I-V characteristics and this was confirmed by the 2D numerical simulations.