In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

In this paper a double edge triggered (DET) filp-flop is proposed which changes its output state at both the positive and the negative edge transitions of the triggering input. DET filp-flop has advantages in terms of speed and power dissipation over single edge triggered (SET) filp-flop has proposed DET flip-flop needs only 12 MOS transistors and can operate at clock speed of 500 MHz. Also, the power dissipation has decreased about 33% in comparison to SET flip-flop.

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.

This paepr presents an algorithm for searching an object in a fast way which contains a continuous moving object in multi-dimensional spatical databases. This algorithm improves the search method of R-tree for the case that a target object is continuously moving in a spatial database. It starts the searching from the current node instead of the root of R-tree. Thus, the algorithm will find the target object from the entries of current node or sibling nodes in the most cases. The performance analysis shows that it is more efficient than the existing algorithm for R-tree when search windows or target objects are continuously moving.

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

For decreasing intersymbol interference (ISI) due to band-limited channels in digitalcommunication, the uses of equalization techniques are necessary. Among the useful adaptive equalization techniques, because of their ease of implementation and nonlinear capabilites, the neural networks have been used as an alternative for effectively dealing with the channel distortion. In this paepr, a complex-valued multilayer percepron is proposed as a nonlinear adaptive equalizer. After the important properties that a suitable complex-valued activation function must possess are discussed, a new complex-valued activation function is developed for the proposed schemes to deal with M-ary QAM signals of any constellation sizes. It has been further proven that by the nonlinear transformation of the proposed function, the correlation coefficient between the real and imaginary parts of input data decreases when they are jointly Gaussian random variables. Lastly, the effectiveness of the proposed scheme is demonstrated by simulations. The proposed scheme provides, compared with the linear equalizer using the least mean squares (LMS) algorith, an interesting improvement concerning Bit Error Rate (BER) when channel distortions are nonlinear.

This paper presents a new maching algorithm by Hopfield Neural Network for 3-D object recognition. In the proposed method, a model object is represented by a set of polygons in a single coordinate. And each polygon is described by a set of features; feature attributes. In case of 3-D object recognition, the scale and poses of the object are important factors. So we propose a strategy for 3-D object recognition independently to its scale and poses. In this strategy, the respective features of the input or the model objects are changed to the startegical constants when they are compared with one another. Finally, we show that the proposed method has a robustness through the results of experiments which included the classification of the input objects and the matching sequence to its 3-D rotation and scale.