마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제25권4호
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  • Pages.41-45
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  • 2018
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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기판 소재에 따른 패널 레벨 패키지 공정 단계별 warpage 해석

Process Induced Warpage Simulation for Panel Level Package

  • 문아영 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과)
  • Moon, Ayoung (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) ;
  • Kim, Sungdong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
  • 투고 : 2018.06.28
  • 심사 : 2018.12.11
  • 발행 : 2018.12.31
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초록

패널 레벨 패키지(Panel Level Package)에서 공정 단계별로 발생하는 휨(warpage)에 대해 유한요소법을 이용하여 전산모사를 진행하였다. $5{\times}5mm^2$ 크기의 실리콘 칩이 총 221개가 포함된 $122.4{\times}93.6mm^2$ 크기의 패널에 대해서 (1) EMC 몰딩, (2) detach core 부착, (3) 가열, (4) 캐리어 분리, (5) 냉각의 5 단계에 대해서 해석을 수행하였으며, 캐리어와 detach core 소재로 유리와 FR4의 조합이 휨 현상에 미치는 영향을 조사하였다. 캐리어 및 detach core의 소재에 따라 공정 단계별로 휨의 경향이 다르게 나타나고 있으나, 최종적으로는 유리를 캐리어로 사용하는 경우에 detach core의 소재와 관계없이 FR4 캐리어에 비해 낮은 휨 값을 나타내었으며 유리 캐리어와 유리 detach core의 조합에서 가장 낮은 휨 값이 관찰되었다.

We have simulated the process induced warpage for panel level package using finite element method. Silicon chips of $5{\times}5mm^2$ were redistributed on $122.4{\times}93.6mm^2$ size panel and the total number of redistributed chips was 221. The warpage at each process step, for example, (1) EMC molding, (2) attachment of detach core, (3) heating, (4) removal of a carrier, and (5) cooling was simulated using ANSYS and the effects of detach core and carrier materials on the warpage were investigated. The warpage behaved complexly depending on the materials for the detach core and carrier. However, glass carrier showed the lower warpage than FR4 carrier regardless of detach core material, and the minimum warpage was observed when the glass was used for the detach core and carrier at the same time.

키워드

MOKRBW_2018_v25n4_41_f0001.png 이미지

Fig. 1. Process flow for panel level package; (1) carrier preparation (2) reconstitution of Si chips (3) EMC molding (4) attachment of detach core (5) detachment of carrier (6) RDL & bump fabrication (7) removal of detach core (8) singulation.

MOKRBW_2018_v25n4_41_f0002.png 이미지

Fig. 2. Panel level package structure (a) top view (b) cross sectional view.

MOKRBW_2018_v25n4_41_f0003.png 이미지

Fig. 3. Total deformation of panel as a function of process step.

MOKRBW_2018_v25n4_41_f0004.png 이미지

Fig. 4. Total deformation at each process step for different detach core/carrier combinations; (1) molding (2) attachment of detach core (3) heating (4) removal of carrier (5) cooling.

Table 1. Process temperature for panel level package.

MOKRBW_2018_v25n4_41_t0001.png 이미지

Table 2. Material properties used in this study.12)

MOKRBW_2018_v25n4_41_t0002.png 이미지

Table 3. Specification for panel level package.

MOKRBW_2018_v25n4_41_t0003.png 이미지

참고문헌

  1. S. E. Kim, and S. D. Kim, "Wafer level Cu-Cu direct bonding for 3D integration", Microelectronic Engineering, 137, 158 (2015). https://doi.org/10.1016/j.mee.2014.12.012
  2. Y. H. Cho, and S. E. Kim, S. D. Kim, "Wafer Level Bonding Technology for 3D Stacked IC", J. Microelectron. Packag. Soc., 20(1), 7 (2013). https://doi.org/10.6117/KMEPS.2013.20.1.007
  3. Philip Garrou, "Wafer Level Chip Scale Packaging (WLCSP): An Overview", IEEE Trans. Adv. Packag., 23(2), 198 (2000). https://doi.org/10.1109/6040.846634
  4. C.-F. Tseng, C.-S. Liu, C.-H. Wu, and D. Yu, "InFO (Wafer Level Integrated Fan-Out) Technology", Proc. 66th Electronic Components and Technology Conference (ECTC), 1, (2016).
  5. T. G. Lim, and D. H. O. S. Wee, "Electrical design for the development of FOWLP for HBM integration", Proc. 68th Electronic Components and Technology Conference (ECTC), 2136, (2018).
  6. F.-C. Hsu, J. Lin, S.-M. Chen, P.-Y. Lin, J. Fang, J.-H. Wang, and S.-P. Jeng, "3D Heterogeneous Integration with Multiple Stacking Fan-Out Package", Proc. 68th Electronic Components and Technology Conference (ECTC), 337, (2018).
  7. T. Braun, K. F. Becker, M. Wohrmann, M. Topper, L. Bottcher, R., Aschenbrenner, and K. D. Lang, "Trends in Fan-out Wafer and Panel Level Packaging" Proc. International Conference on Electronics Packaging (ICEP), Japan, 325 (2017).
  8. J. Y. Kim, I. J. Choi, J. H. Park, J.-E. Lee, T. S. Jeong, J. S Byun, Y. G. Ko, K. H. Hur, D.-W. Kim, and K. S. Oh, "Fanout Panel Level Package with Fine Pitch Pattern", Proc. 68th Electronic Components and Technology Conference (ECTC), 1, (2018).
  9. K. Kikuchi, Y. Nedzu, and T. Sugino, "Warpage Analysis with Newly Molding Material of Fan-Out Panel Level Packagingand the Board Level Reliability Test Results", Proc. 68th Electronic Components and Technology Conference (ECTC), 973, (2018).
  10. J. H. Lau, M. Li, D. Tian, N. Fan, E. Kuah, W. Kai, M. Li, J. Hao, Y. M. Cheung, Z. Li, H. T. Kim, R. Beica, T. Taylor, C.-T. Ko, H. Yang, Y.-H. Chen, S. P. Lim, N. C. Lee, J. Ran, C. Xi,K. S. Wee, and Q. Yong, "Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging", IEEE Trans. Compon. Packaging Manuf. Technol., 7(10), 1729 (2017). https://doi.org/10.1109/TCPMT.2017.2715185
  11. G. T. Kim, and D. I. Kwon, "Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis", J. Microelectron. Packag. Soc., 25(1), 41 (2018). https://doi.org/10.6117/KMEPS.2018.25.1.041
  12. T. Lin, F. Hou, H. Liu, D. Pan, F. Chen, J. Li, H. Zhang, and L. Cao, "Warpage simulation and experiment for panel level fan-out package", IEEE CPMT Symposium Japan (ICSJ), 129, (2016).