Fig. 1. Process flow for panel level package; (1) carrier preparation (2) reconstitution of Si chips (3) EMC molding (4) attachment of detach core (5) detachment of carrier (6) RDL & bump fabrication (7) removal of detach core (8) singulation.
Fig. 2. Panel level package structure (a) top view (b) cross sectional view.
Fig. 3. Total deformation of panel as a function of process step.
Fig. 4. Total deformation at each process step for different detach core/carrier combinations; (1) molding (2) attachment of detach core (3) heating (4) removal of carrier (5) cooling.
Table 1. Process temperature for panel level package.
Table 2. Material properties used in this study.12)
Table 3. Specification for panel level package.
참고문헌
- S. E. Kim, and S. D. Kim, "Wafer level Cu-Cu direct bonding for 3D integration", Microelectronic Engineering, 137, 158 (2015). https://doi.org/10.1016/j.mee.2014.12.012
- Y. H. Cho, and S. E. Kim, S. D. Kim, "Wafer Level Bonding Technology for 3D Stacked IC", J. Microelectron. Packag. Soc., 20(1), 7 (2013). https://doi.org/10.6117/KMEPS.2013.20.1.007
- Philip Garrou, "Wafer Level Chip Scale Packaging (WLCSP): An Overview", IEEE Trans. Adv. Packag., 23(2), 198 (2000). https://doi.org/10.1109/6040.846634
- C.-F. Tseng, C.-S. Liu, C.-H. Wu, and D. Yu, "InFO (Wafer Level Integrated Fan-Out) Technology", Proc. 66th Electronic Components and Technology Conference (ECTC), 1, (2016).
- T. G. Lim, and D. H. O. S. Wee, "Electrical design for the development of FOWLP for HBM integration", Proc. 68th Electronic Components and Technology Conference (ECTC), 2136, (2018).
- F.-C. Hsu, J. Lin, S.-M. Chen, P.-Y. Lin, J. Fang, J.-H. Wang, and S.-P. Jeng, "3D Heterogeneous Integration with Multiple Stacking Fan-Out Package", Proc. 68th Electronic Components and Technology Conference (ECTC), 337, (2018).
- T. Braun, K. F. Becker, M. Wohrmann, M. Topper, L. Bottcher, R., Aschenbrenner, and K. D. Lang, "Trends in Fan-out Wafer and Panel Level Packaging" Proc. International Conference on Electronics Packaging (ICEP), Japan, 325 (2017).
- J. Y. Kim, I. J. Choi, J. H. Park, J.-E. Lee, T. S. Jeong, J. S Byun, Y. G. Ko, K. H. Hur, D.-W. Kim, and K. S. Oh, "Fanout Panel Level Package with Fine Pitch Pattern", Proc. 68th Electronic Components and Technology Conference (ECTC), 1, (2018).
- K. Kikuchi, Y. Nedzu, and T. Sugino, "Warpage Analysis with Newly Molding Material of Fan-Out Panel Level Packagingand the Board Level Reliability Test Results", Proc. 68th Electronic Components and Technology Conference (ECTC), 973, (2018).
- J. H. Lau, M. Li, D. Tian, N. Fan, E. Kuah, W. Kai, M. Li, J. Hao, Y. M. Cheung, Z. Li, H. T. Kim, R. Beica, T. Taylor, C.-T. Ko, H. Yang, Y.-H. Chen, S. P. Lim, N. C. Lee, J. Ran, C. Xi,K. S. Wee, and Q. Yong, "Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging", IEEE Trans. Compon. Packaging Manuf. Technol., 7(10), 1729 (2017). https://doi.org/10.1109/TCPMT.2017.2715185
- G. T. Kim, and D. I. Kwon, "Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis", J. Microelectron. Packag. Soc., 25(1), 41 (2018). https://doi.org/10.6117/KMEPS.2018.25.1.041
- T. Lin, F. Hou, H. Liu, D. Pan, F. Chen, J. Li, H. Zhang, and L. Cao, "Warpage simulation and experiment for panel level fan-out package", IEEE CPMT Symposium Japan (ICSJ), 129, (2016).