JSTS:Journal of Semiconductor Technology and Science

  • 제7권3호
  • /
  • Pages.209-213
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  • 2007
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Compact Gate Capacitance Model with Polysilicon Depletion Effect for MOS Device

  • Abebe, H. (University of Southern Califormia Information Science Institute, MOSIS service) ;
  • Morris, H. (San Jose State University) ;
  • Cumberbatch, E. (Claremont Graduate University) ;
  • Tyree, V. (University of Southern Califormia Information Science Institute, MOSIS service)
  • 발행 : 2007.09.30
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초록

The MOS gate capacitance model presented here is determined by directly solving the coupled Poisson equations on the poly and silicon sides, and includes the polysilicon (poly) gate depletion effect. Our compact gate capacitance model exhibits an excellent fit with measured data and parameter values extracted from data are physically acceptable. The data are collected from 0.5, 0.35, 0.25 and $0.18{\mu}m$ CMOS technologies.

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참고문헌

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