• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.225-231
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• 2010

In this paper, we investigate the channel thermal noise in nanoscale MOSFETs. Simple analytical model of thermal noise factor in nanoscale MOSFETs is presented and it is verified with accurately measured noise data. The noise factor is expressed in terms of the channel conductance and the electric field in the gradual channel region. The proposed noise model can predict the channel thermal noise behavior in all operating bias regions from the long-channel to nanoscale MOSFETs. From the measurement results, we observed that the thermal noise model for the long-channel MOSFETs does not always underestimate the short-channel thermal noise.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.114-118
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• 1994

To resolve thd discrepancy between the existing channel thermal noise theory of MOSFETs and a new theory called the stady-state Nyquist theorem, we have measured the channel thermal noise of specially designed MOSFETs with both uniform and nonuniform channels. the experimental results clearly show that the correct theory of the channel thermal nois in MOSFETs should be the steady-state Nyquist theorem.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.188-189
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• 2017

There has been a growing demand for power semiconductor switches equipped with high-voltage blocking capability of kV range and fast-switching characteristics of ns range in various plasma application. This paper investigates the application of SiC MOSFETs in the particular plasma application which requires the blocking voltage of 4.5kV and the switching transient time of less than 100ns. In order to meet the required blocking voltage, the series connection of multiple SiC MOSFETs is adopted in this paper. Also, snubber capacitors are employed to equalize the voltage sharing among the series connected SiC MOSFETs. The simulation and experimental result successfully verifies the application of SiC MOSFETs and snubber capacitors in the plasma application requiring high-voltage and fast-switching load dynamics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.73-74
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• 2007

We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.245-248
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• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.27-31
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• 2004

Models and simulations of gate tunneling current for thinoxide MOSFETs and Double-Gate SOIs are discussed. A guideline in design of leaky MOS capacitors is proposed and resonant gate tunneling current in DG SOI simulated based on quantum-mechanicalmodels. Gate tunneling current in fully-depleted, double-gate SOI MOSFETs is characterized based on quantum-mechanical principles. The simulated $I_G-V_G$ of double-gate SOI has negative differential resistance like that of the resonant tunnel diodes.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.234-237
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• 2013

본 논문에서는 실리콘 나노선 구조를 갖는 모스펫 (Metal-Oxide-Semiconductor Field Effect Transistors, MOSFETs)과 쇼트키 장벽 트랜지스터 (Schottky-Barrier(SB) MOSFETs, SB-MOSFETs)의 전기적인 특성을 양자역학적 시뮬레이션 계산을 통해 비교하였다. 쇼트키 장벽 높이 (Schottky Barrier, ${\phi}_{SBH}$)에 따른 SB-MOSFETs의 터널링 특성을 분석하고, 소스/드레인 (S/D) 길이가 변함에 따라 달라지는 S/D 저항을 계산하여, ${\phi}_{SBH}$가 0eV인 SB-MOSFETs의 On과 Off $I_D$ 비율 ($I_{ON}/I_{OFF}$)이 MOSFETs보다 개선될 수 있음을 보였다.