• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.1
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• pp.71-76
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• 2023

Recently, a memory management strategy that utilizes read and write references separately is attracting attention. This is due to the emergence of new storage media with asymmetric read/write latencies and different read/write access characteristics of software. Existing research assumes that operating systems can differentiate between read/write references that occur on each memory page, but most memory architectures do not support a way to distinguish them. Unlike previous studies, this paper proposes a software method that reflects the read/write characteristics of page references by utilizing the reference and modified bits of each page. Simulations show that the proposed policy has almost similar effects to existing studies with hardware support.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.180-181
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• 2002

수직기록매체에서 기록 밀도가 증가하기 위해서는 bit의 크기를 줄여야 하고, 이를 위해서는 writing head의 width와 thickness를 줄여야 한다. 그러나 head의 크기가 줄어들면 기록층의 자화를 반전시키기에 충분한 write field를 얻지 못한다. 이를 극복하기 위해 head의 tip부분을 trimming을 하여 작은 pole tip 크기를 가지면서도 큰 write field를 얻고, 여분의 magnetic field를 얻기 위해 soft underlayer를 도입하는 이중층 수직기록 매체가 제안되고 있다. (중략)

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.752-759
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• 2010

In this paper, we propose differential-logging method to improve the performance of RMW(Read Modify Write) operations of DDR-SSD based software RAID. Small writes that are frequently occurred in enterprise applications are main factor to degrade the performance of RAID5. Once a block is updated in RAID5, the parity block of the block must be updated to maintain consistency of parity. Therefore, to process a small write request, we need to read its parity block stored in disk, read old data, perform XOR operation, and write updated data and parity block. Several methods for hard disk based software RAID are proposed to solve the small write problems in RAID 5. Ln this paper, we propose a differential-logging method which carefully considers the DDR-SSD to solve the small write problem in RAID 5. We show that our proposed method out performs the existing software RAID in LINUX through simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.23-30
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• 2016

We report a STT-MRAM write-scheme, in which the length of the write-pulse is determined dynamically by sensing the status of MTJ cells. The proposed scheme can reduce the power consumption by eliminating unnecessary writing current after the switching has occurred. We also propose a reference cell design, which is optimized for the use in write-circuits. The performance of the proposed circuit was verified by SPICE level simulations of the circuit implemented in a $0.13{\mu}m$ CMOS process.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.69-72
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• 2000

This paper describes an SRAM write driver circuit which dissipates small power. The write driver utilizes a dual sized transistor structure to reduce operating current in the write cycle. In the case of higher voltage comparing to Vcc, only one transistor is active, while in the case of low Vcc two transistors are active so as to deliver the current twice. Thus though with the high voltage operation, the power consumption is reduced with keeping the speed in a given specification. Simulation results have verified the functionality of the new circuit and write power is reduced by 7 % per bit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.330-338
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• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.771-774
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• 2014

지난 몇 년간 스마트폰은 굉장히 빠른 속도로 발전하면서 생활 속에서 큰 비중을 차지하고 있다. 이러한 스마트폰에는 에너지 효율, 크기, 속도 면에서 모바일 기기에 적합한 Flash storage가 탑재되고 있다. 이 논문에서는 스마트폰에 탑재된 Flash storage를 기반으로 한 버퍼 교체 알고리즘들 가운데 Spatial Clock 알고리즘에 초점을 맞추고 있다. 그리고 이 알고리즘이 Video Streaming workload에서 성능 발휘를 하지 못한다는 점을 해결하기 위해 SWSC(Sequential Write Spatial Clock) 알고리즘을 제안하였다. 이 알고리즘은 dirty 페이지들이 연속적인 경우 sequential write를 수행한다. 따라서 write 수행시간을 줄일 수 있고 결과적으로 Video Streaming workload에서도 좋은 성능을 발휘할 수 있다.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.79-86
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• 2019

For decades, in-memory data structures have been designed for DRAM-based main memory that provides symmetric read/write performances and has no limited write endurance. However, such data structures provide sub-optimal performance for NVM as it has different characteristics to DRAM. With this motivation, we rethink a conventional red-black tree in terms of its efficacy under NVM settings. The original red-black tree constantly rebalances sub-trees so as to export fast access time over dataset, but it inevitably increases the write traffic, adversely affecting the performance for NVM with a long write latency and limited endurance. To resolve this problem, we present a variant of the red-black tree called a hierarchical balanced binary search tree. The proposed structure maintains multiple keys in a single node so as to amortize the rebalancing cost. The performance study reveals that the proposed hierarchical binary search tree effectively reduces the write traffic by effectively reaping the high capacity of NVM.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.21-23
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• 2013

Static Random Access Memory (SRAM) using CMOS technology has many advantages. It does not need to refresh every certain time, as a result, the speed of SRAM is faster than Dynamic Random Access Memory (DRAM). This is the reason why SRAM is widely used in almost processors and system on chips (SoC) which require high processing speed. Two basic operations of SRAM are read and write. We consider two basic factors, including the accuracy of read and write operations and the speed of these operations. In our paper, we propose the read and write assist circuits for SRAM. By adding a power control circuit in SRAM, the write operation performed successfully with low error ratio. Moreover, the value in memory cells can be read correctly using the proposed pre-charge method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.56-61
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• 2023

The characteristics of write discharge were investigated when the conventional driving method with the unipolar sustain voltages, and the single sustain driving method applying the bipolar sustain voltage were applied in an AC plasma display. In the case of having a single sustain waveform, the strength of the write discharge is weakened compared to the conventional driving method during the address period, because the wall charge inside the panel is more dissipated by the lower scanning voltage. In the driving method with a single sustain waveform, the bias voltage of the other electrodes was changed to improve the write discharge characteristics. As a result, the intensity of the discharge was enhanced by 32% and the delay time was shortened by 60 ㎲.