• Journal of the Korean Vacuum Society
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• v.18 no.3
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• pp.203-207
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• 2009

Copper is known as a replacement for aluminum wire which is used for semiconductor. Because specific resistance of Cu ($1.67{\mu}{\Omega}$-cm) is lower than that of Al ($2.66{\mu}{\Omega}$-cm), Cu reduce RC delay time. Although melting point of Cu($1085^{\circ}C$) is higher than melting point of Al, Cu have characteristic to easily react with Silicon(Si) in low temperature, and it isn't good at adhesive strength with Si. For above these reason, research of diffusion barrier to prevent reaction between Cu and Si and to raise adhesive strength is steadily advanced. Our study group have researched on W-C-N (tungsten-carbon-nitrogen) Diffusion barrier for preventing diffusion of Cu through semiconductor. By recent studies, It's reported that W-C-N diffusion barrier can even precent Cu and Si diffusing effectively at high temperature. In this treatise, we vaporized different proportion of N into diffusion barrier to research Cu's Electromigration based on the results and studied surface hardness in the heat process using nano scale indentation system. We gain that diffusion barrier containing nitrogen is more stable for Cu's electromigration and has stronger surface hardness in heat treatment process.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• Journal of Advanced Navigation Technology
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• v.9 no.1
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• pp.71-78
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• 2005

Nowadays, the demand of HPI(High-speed Portable Internet) has been gradually increased to support the various services of high speed wire line internet such as xDS. HPI can support high speed internet in anyplace, anytime. For successful development of HPI, the performance should be evaluated according to the cell size and/or the number of users and cell design should be carried out based on these criteria. The previous cellular systems using CDMA technique focus on the establishment of link based on power control but HPI systems consider the QoS (Quality of Service) and its performance based on the scheduling technique. The results from the system level simulation show that the throughput is sensitive to the cell size and the number of users has little impact on it. Moreover, the variation of service delay is more sensitive to the number of users but less to the cell size.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.10
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• pp.4296-4301
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• 2011

Gantry loader which is also called as gantry robot is a kind of cartesian coordinate robot with two or more linear motions. A conventional gantry system has cableveyor for protecting power and signal cables, but the use of cableveyor makes a delay of work due to frequent repairing for its aging. This study reports that a wireless gantry loader is able to be operated without a power line for power transmission or a signal cable for motion control. The wireless gantry loader enables a convenient maintenance and a stable productivity by the reduction of wire broken from fatigue. The developed loader system is controlled by PC-based motion controller and is communicated by wireless LAN devices. The line from a power source to the loader system was substituted by attaching trolley bar on the traveling beam. The loader system was designed to be moved with high speed and high repeatability, and the motion was observed continuously by monitoring system in the PC-based controller. The maximum speed and the repeatability for the transferring and loading axes are 200 m/min, 60 mm and 100 m/min, 40 mm respectively.

• Journal of Internet Computing and Services
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• v.17 no.4
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• pp.11-17
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• 2016

In this paper, we proposed a multi-viewer system with multiple HD cameras based AVB(Audio Video Bridge) ethernet cable using IP networking, and FPGA(Xilinx Zynq 702) for bus safety systems. This AVB (IEEE802.1BA) system can be designed for the low latency based on FPGA, and transmit real-time with HD video and audio signals in a vehicle network. The proposed multi-viewer platform can multiplex H.264 video signals from 4 wide-angle HD cameras with existed ethernet 1Gbps. and 2-wire 100Mbps cables. The design of Zynq 702 based low latency to H.264 AVC CODEC was proposed for the minimization of time-delay in the HD video transmission of car area network, too. And the performance of PSNR(Peak Signal-to-noise-ratio) was analyzed with the reference model JM for encoding and decoding results in H.264 AVC CODEC. These PSNR values can be confirmed according the theoretical and HW result from the signal of H.264 AVC CODEC based on Zynq 702 the multi-viewer with multiple cameras. As a result, proposed AVB multi-viewer platform with multiple cameras can be used for the surveillance of audio and video around a bus for the safety due to the low latency of H.264 AVC CODEC design.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.12
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• pp.1039-1047
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• 2017

This paper presents a test development of a Fly-By-Wireless flight control system for a fixed-wing unmanned aerial vehicle (UAV). Fly-By-Wireless system (FBWLS) refers to a system that uses a wireless network instead of a wired network to connect sensors and actuators with a flight control computer (FCC), reducing considerable amount of wires. FBWLS enables to design a much lighter aircraft along with decreased maintenance time and cost. In this research we developed a Zigbee-based FWBLS UAV in which sensors (GPS and AHRS) are wirelessly connected via a FCC to aileron and elevator servo motors. In order to see the effect of time delay due to wireless signal on the flight stability of the UAV, several flight tests were conducted. From the tests, it was confirmed that the effect is minor by comparing the flight response of the FBWLS with the corresponding Fly-By-Wire system.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.843-850
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• 2004

As mobile devices prevail, requests for various services using mobile devices have increased. Requests for application services that require large data space such as multimedia, game and database [1] specifically have greatly increased. However, mobile appliances have difficulty in applying various services like a wire environment, because the storage capacity of one is not enough. Therefore, research (5) which provides remote storage service for mobile appliances using iSCSI is being conducted to overcome storage space limitations in mobile appliances. But, when iSCSI is applied to mobile appliances, iSCSI I/O performance drops rapidly if a iSCSI client moves from the server to a far away position. In the case of write operation, $28\%$ reduction of I/O performance occurred when the latency of network is 64ms. This is because the iSCSI has a structural quality that is very .sensitive to delay time. In this paper, we will introduce an intermediate target server and localize iSCSI target to improve the shortcomings of iSCSI performance dropping sharply as latency increases when mobile appliances recede from a storage server.