• Title/Summary/Keyword: wire delay

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Improvement of Time Synchronization of SpaceWire Network through Time-Code Extension (타임코드 확장을 통한 스페이스와이어 네트워크의 시각 동기화 성능 개선)

  • Ryu, Sang-Moon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.4
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    • pp.724-730
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    • 2017
  • SpaceWire invented for spacecrafts has Time-Code defined for time synchronization over SpaceWire network. A Time-Code suffers transmission delay of 14[bit-period] and jitter up to 10[bit-period] whenever it passes through a SpaceWire link, which is the primary cause of time synchronization error. This work presents a simple method to improve the time synchronization which uses two extended Time-Codes. Nodes on a SpaceWire network can find how much delay and jitter a received Time-Code has suffered while it passes through the network, and they can correct time synchronization error with this information. The proposed method was validated in a simulation environment developed based on OMNeT++. The simulation result showed that time synchronization error less than a few bit-periods can be achieved. The proposed method is cost effective and suitable for small-scale SpaceWire network systems.

Time Synchronization over SpaceWire Network using Hop Count Information (홉 카운트 정보를 이용한 스페이스와이어 네트워크 시각동기화 방안)

  • Ryu, Sang-Moon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.715-718
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    • 2016
  • SpaceWire invented for on-board data handling in a spacecraft has Time-Code defined for time synchronization over SpaceWire network. Delay and jitter of the transmission of Time-Code caused when a Time-Code travels through a network are the main reasons of time synchronization error. This work proposes a scheme that can reduce the time synchronization error by using extended Time-Codes. The proposed scheme can remove both transmission jitter and transmission delay. The scheme will be validated in a simulation environment built with OMNeT++.

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Chaos synchronization of Chuas circuit with equivalent wire and wireless transmission (등가 유무선 선로를 가진 Chua 회로에서의 카오스 동기화)

  • 배영철
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2000.11a
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    • pp.227-230
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    • 2000
  • Chuas circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper, a transmitter and a receiver using two identical Chuas circuits are proposed and synchronizations of a equivalent wire and wireless power line are investigated. Since the synchronization of the equivalent wire and wireless system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. As a result, the chaos synchronization has delay characteristics in the equivalent wire and wireless transmission system caused by the line parameters L and C.

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Redundancy Management of Brake-by-wire System using a Message Scheduling (메시지 스케줄링을 이용한 Brake-by-wire 시스템의 Redundancy Management)

  • Yune, J. W.;Kim, K. W.;Kim, T. Y.;Kim, J. G.;Lee, S.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2000.11a
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    • pp.717-720
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    • 2000
  • Event-driven communication protocols such as CAN(Controller Area Network) have inherent packet delays due to the contention process for the use of network medium. These delays are stochastic in nature because most packets arrive at random time instants. The stochastic property of the delay adversely influences the control system's performance in terms of stability, responsiveness and steady-state error. Another problem for safety-critical application such as brake-by-wire systems is the reliability of the communication modules that can fail abruptly. This paper deals with two methods to overcome the above problems : (i) scheduling method that can maintain packet delays under some acceptable level, and (ii) redundancy management of communication modules that prescribes dual-redundancy modules' behavior when one of them fails.

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Chaos Synchronization of Chua's Circuit with Transmission Line (전송선로를 가진 Chua 회로에서의 카오스 동기화)

  • Ko, Jae-Ho;Bae, Young-Chul;Yim, Hwa-Young
    • Proceedings of the KIEE Conference
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    • 1997.07b
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    • pp.633-635
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    • 1997
  • In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and a wire synchronizations are investigated. As several problems have been found in both the drive-response synchronization and the coupled synchronization in the previous researches, a new drive-coupled synchronization theory is proposed that can be applicable to wire communication. Since the synchronization of the wire transmission system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. As a result, the chaos synchronization has delay characteristics in the wire transmission system caused by the line parameters L and C.

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Design of Low Power and High Speed NCL Gates (저전력 고속 NCL 비동기 게이트 설계)

  • Kim, Kyung Ki
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.2
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    • pp.112-118
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    • 2015
  • Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

Transient Heat Transfer from a Suddenly Heated Verical Thin Wire (수직열선 근처의 과도 열전달 에 관한 실험적 연구)

  • 최만수;유정열;노승탁
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.7 no.4
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    • pp.461-468
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    • 1983
  • The series of experiments have been performed to study the transient heat transfer in air from a suddenly heated vertical thin wire. A platinum wire has been used as a resistance thermometer as well as a heating element to eliminate the disturbances in the measurements. The measured temperature as a function of time is compared with the calculated transient temperature with the aid of a pure conduction equation. The overshoot phenomena in terms of the Nusselt numbers have been detected and it is reasonable to define the delay time at which the onset of convection heat transfer occurs. The measured data are compared with the existing steady-state data and the agreements are reasonable within the comparable ranges.

Chaos secure synchronization with equivalent transmission line of chaos circuit (등가 전송선로를 가진 카오스 회로질서의 카오스 동기화)

  • Bae, Young-Chul;Yim, Wha-Young
    • Proceedings of the KIEE Conference
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    • 1999.07b
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    • pp.721-723
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    • 1999
  • Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and a equivalent wire synchronizations are investigated Since the synchronization of the wire transmission system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. As a result, the chaos synchronization has delay characteristics in the wire transmission system caused by the line parameters L and C.

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An Analysis Technique for Interconnect Circuits with Multiple Driving Gates in Deep Submicron CMOS ASICs (Deep Submicron CMOS ASIC에서 다중 구동 게이트를 갖는 배선회로 해석 기법)

  • Cho, Kyeong-Soon;Byun, Young-Ki
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.12
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    • pp.59-68
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    • 1999
  • The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

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A Study of the Behavior of Droplet Impacting on a Horizontal Wire (수평 와이어와 충돌하는 액적 거동에 관한 연구)

  • Kang, W.J.;Kim, J.Y.;Park, J.H.;Kang, B.S.
    • Journal of ILASS-Korea
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    • v.25 no.3
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    • pp.103-110
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    • 2020
  • In this study, the behavior of water droplet impacting on a thin horizontal wire was visualized by time-delay photography. The impact behavior modes, critical capture speed and trapped mass were analyzed by changing the droplet size, velocity, wire diameter and eccentricity ratio. As the Weber number increased, the hanging, merging, and splitting modes appeared sequentially for the case of central impact, and the hanging and non-splitting modes appeared for the case of off-center impact. The boundary We number of each mode was affected by the diameter ratio. The critical capture speed was affected much by the degree of eccentricity. For all diameter ratios, it was higher for the case of central impact than for off-center impact. The trapped mass was larger for the case of central impact than for off-center impact and it increased with the smaller We number and the larger diameter ratio.