• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1098-1103
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• 2013

A low-noise amplifier(LNA) using series RLC matching network and resistive feedback at 8 GHz is presented. Inductive degeneration is used for the input matching with which the proposed LNA shows quite a wide bandwidth in terms of $S_{21}$. An equivalent circuit model is deduced for input matching by conversion from parallel circuit to series resonant circuit. By exploiting the resistive feedback and series RLC input matching, fully integrated LNA achieves maximum $S_{21}$ of 8.5 dB(peak to -3 dB bandwidth is about 3.5 GHz) noise figure of 5.9 dB, and IIP3 of 1.6 dBm while consuming 7 mA from 1.2 V supply.

• Journal of information and communication convergence engineering
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• v.16 no.4
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• pp.252-257
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• 2018

A wideband double radiator circular disc annular monopole antenna is proposed is this work. The radiators are etched on the surfaces of two Taconic TLY-5 substrates with a circular hole cut out of each of the radiators initially at the centers of the radiators with subsequent downward displacement of the holes. The antenna is designed with a two-step feeding transformer system for impedance matching between the input power source supplied by a $50-{\Omega}$ SMA connector and the monopole radiators. The transformer system improves the bandwidth performance at higher frequencies. The proposed antenna achieves a wideband having the capability of working between 0.645 and 18.775 GHz, corresponding to a -10 dB bandwidth of 186.7% with gain ranging from 0.95 to 8.26 dBi. In comparison to other metal disc planar monopole antennas, the proposed antenna has a small total size width due to the size of the ground plane, which has a diameter 100 mm. The frequency range of the antenna provides applications in global positioning systems, mobile communications, ultra-wideband short distance communications, and wireless computer networks.

• Journal of electromagnetic engineering and science
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• v.16 no.4
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• pp.241-247
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• 2016

This paper proposes the design and measurement of a 6-18 GHz front-end receiver module that has been combined into a one- channel output from a two-channel input for electronic warfare support measures (ESM) applications. This module includes a limiter, high-pass filter (HPF), power combiner, equalizer and amplifier. This paper focuses on the design aspects of reducing the noise figure (NF) and matching the phase and amplitude. The NF, linear equalizer, power divider, and HPF were considered in the design. A broadband receiver based on a combined configuration used to obtain low NF. We verify that our receiver module improves the noise figure by as much as 0.78 dB over measured data with a maximum of 5.54 dB over a 6-18 GHz bandwidth; the difference value of phase matching is within $7^{\circ}$ between ports.

• ETRI Journal
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• v.34 no.4
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• pp.485-491
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• 2012

In this paper, the implementations of a $0.1{\mu}m$ gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single-chip receiver for 70/80 GHz point-to-point communications are presented. To obtain high-gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five-stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five-stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of -1.5 dBm to 1.5 dBm. Finally, a single-chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of -21 dBm.

• The Journal of the Acoustical Society of Korea
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• v.25 no.1
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• pp.21-29
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• 2006

In this Paper a split bandwidth wideband speech coder and its highband coding method are Proposed. The coder uses a split-band approach. where the wideband input speech signal is split into two equal frequency bands from 0-4kHz and 4-8kHz. The lowband and the highband are coded respectively by the 11.8kb/s G.729 Annex E and the proposed coding method. After the LPC analysis, the highband is divided by two modes according to the properties of signals. In stationary mode. the highband signals are compressed by the mixture excitation model; CELP algorithm and W (Matching Pursuit) algorithm. The others are coded by the only CELP algorithm. We compare the performance of the new wideband speech coder with that of G.722 48kbps SB-ADPCM and G.722.2 12.85kbps in a subjective method. The simulation results show that the Performance of the proposed wideband speech coder has better than that of 48kbps G.722 and no better than that of 12.85kbps G.722.2.

• ETRI Journal
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• v.29 no.5
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• pp.670-672
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• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.1
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• pp.76-80
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• 2011

This paper has proposed a 3~5 GHz low-power and wideband LNA(Low Noise Amplifier), which has been implemented in a 0.18-${\mu}m$ CMOS technology. The proposed LNA has basically the noise-cancelling topology to achieve a balun-function, wideband input matching, and relative low noise figure. In addition, it has utilized a 2nd-order LC-band-pass filter(BPF) as its output load to achieve higher power gain and lower noise figure with the lowest dc power consumption among previously reported works. The proposed amplifier consumes only 3.94 mA from a 1.8 V supply voltage. The simulation results show a power gain of more than +17 dB, a noise figure of less than +4 dB, and an input IP3 of -15.5 dBm.