• Title/Summary/Keyword: wide bandgap

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HVPE growth of Mg-doped AlN epilayers for high-performance power-semiconductor devices (고효율 파워 반도체 소자를 위한 Mg-doped AlN 에피층의 HVPE 성장)

  • Bae, Sung Geun;Jeon, Injun;Yang, Min;Yi, Sam Nyung;Ahn, Hyung Soo;Jeon, Hunsoo;Kim, Kyoung Hwa;Kim, Suck-Whan
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.27 no.6
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    • pp.275-281
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    • 2017
  • AlN is a promising material for wide band gap and high-frequency electronics device due to its wide bandgap and high thermal conductivity. AlN has advantages as materials for power semiconductors with a larger breakdown field, and a smaller specific on-resistance at high voltage. The growth of a p-type AlN epilayer with high conductivity is important for a manufacturing an AlN-based applications. In this paper, Mg doped AlN epilayers were grown by a mixed-source HVPE. Al and Mg mixture were used as source materials for the growth of Mg-doped AlN epilayers. Mg concentration in the AlN was controlled by modulating the quantity of Mg source in the mixed-source. Surface morphology and crystalline structure of AlN epilayers with different Mg concentrations were characterized by FE-SEM and HR-XRD. XPS spectra of the Mg-doped AlN epilayers demonstrated that Mg was doped successfully into the AlN epilayer by the mixed-source HVPE.

Spectral Response of $TiO_{2}$/Se : Te Heterojunction for Color Sensor (컬러센서를 위한 $TiO_{2}$/Se : Te 이종접합의 스펙트럼 응답)

  • Woo, Jung-Ok;Park, Wug-Dong;Kim, Ki-Wan;Lee, Wu-Il
    • Journal of Sensor Science and Technology
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    • v.2 no.1
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    • pp.101-108
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    • 1993
  • $TiO_{2}$/Se : Te heterojunction for color sensor has been fabricated by RF reactive sputtering and thermal evaporation methods onto glass substrate. The optimum deposition condition of $TiO_{2}$ films was such that RF power was 120 W, substrate temperature was $100^{\circ}C$, oxygen concentration was 50%, working pressure was 50 mTorr for the $TiO_{2}$ film thickness of $1000{\AA}$. In this case, the optical transmittance of $TiO_{2}$ film at 550 nm-wavelength was 85%, resistivity was $2{\times}10^9{\Omega}{\cdot}cm$, refractive index was 2.3, and optical bandgap was 3.58 eV. The composition ratio of 0 to Ti by AES analysis was 1.7. When $TiO_{2}$ films were annealed at $400^{\circ}C$ for 30 min. in $O_{2}$ ambient, the optical transmittance of $TiO_{2}$ films at the wavelength range of $300{\sim}580$ nm was improved from 0 to 25%. When Se : Te films were annealed at $190^{\circ}C$ for 1 min., photosensitivity under illumination of 1000 lux was 0.75. The optical bandgap of Se : Te films was 1.7 eV. The structures of Se : Te films were the hexagonal with (100) and (110) orientation. The spectral response of a-Se was improved by the addition of Te, especially in the long wavelength region. The $TiO_{2}$/Se : Te heterojunction showed wide spectral response, and more improved one than that of a-Si film in the blue light region.

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Mixed-mode simulation of transient characteristics of 4H-SiC DMOSFETs - Impact off the interface changes (Mixde-mode simulation을 이용한 4H-SiC DMOSFETs의 계면상태에서 포획된 전하에 따른 transient 특성 분석)

  • Kang, Min-Seok;Choe, Chang-Yong;Bang, Wook;Kim, Sang-Chul;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.55-55
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    • 2009
  • Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

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Electrochemical Characteristic Change of Cr-doped Li4Ti5O12 due to Different Water Solubility of Dopant Precursors (도판트 프리커서의 용해도 차이에 의한 Cr-doped Li4Ti5O12의 전기화학적 특성 변화)

  • Yun, Su-Won;Song, Hannah;Kim, Yong-Tae
    • Journal of the Korean Electrochemical Society
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    • v.18 no.1
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    • pp.17-23
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    • 2015
  • $Li_4Ti_5O_{12}$ (LTO) have attracted much attention of researchers in the field of energy storage, because of their excellent stability for electric vehicle application. A main drawback of LTO is however their insulating nature due to the wide bandgap, which should be addressed to enhance the battery performance. In this study, we investigated the effect of water solubility of dopant precursor on the electrochemical characteristics of conducting LTO prepared by doping with $Cr^{3+}$ ions with the well-known wet-mixing method. The solubility of dopant precursor directly affected the morphology and the phase of doped LTO, and therefore their battery performance. In the case of employing the most soluble dopant precursor, $Cr(NO_3)_2$, the doped LTO demonstrated a markedly enhanced discharge capacity at high C-rate (130mAh/g @ 10C), which is about 2 times higher value than that of bare LTO.

저온 공정 온도에서 $Al_2O_3$ 게이트 절연물질을 사용한 InGaZnO thin film transistors

  • 우창호;안철현;김영이;조형균
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.11-11
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    • 2010
  • Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

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Fabrication of P-type Transparent Oxide Semiconductor SrCu2O2 Thin Films by RF Magnetron Sputtering (RF 마그네트론 스퍼터링을 이용한 p 타입 투명전도 산화물 SrCu2O2 박막의 제조)

  • Seok, Hye-Won;Kim, Sei-Ki;Lee, Hyun-Seok;Lim, Tae-Young;Hwang, Jong-Hee;Choi, Duck-Kyun
    • Korean Journal of Materials Research
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    • v.20 no.12
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    • pp.676-680
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    • 2010
  • Most TCOs such as ITO, AZO(Al-doped ZnO), FTO(F-doped $SnO_2$) etc., which have been widely used in LCD, touch panel, solar cell, and organic LEDs etc. as transparent electrode material reveal n-type conductivity. But in order to realize transparent circuit, transparent p-n junction, and introduction of transparent p-type materials are prerequisite. Additional prerequisite condition is optical transparency in visible spectral region. Oxide based materials usually have a wide optical bandgap more than ~3.0 eV. In this study, single-phase transparent semiconductor of $SrCu_2O_2$, which shows p-type conductivity, have been synthesized by 2-step solid state reaction at $950^{\circ}C$ under $N_2$ atmosphere, and single-phase $SrCu_2O_2$ thin films of p-type TCOs have been deposited by RF magnetron sputtering on alkali-free glass substrate from single-phase target at $500^{\circ}C$, 1% $H_2$/(Ar + $H_2$) atmosphere. 3% $H_2$/(Ar + $H_2$) resulted in formation of second phases. Hall measurements confirmed the p-type nature of the fabricated $SrCu_2O_2$ thin films. The electrical conductivity, mobility of carrier and carrier density $5.27{\times}10^{-2}S/cm$, $2.2cm^2$/Vs, $1.53{\times}10^{17}/cm^3$ a room temperature, respectively. Transmittance and optical band-gap of the $SrCu_2O_2$ thin films revealed 62% at 550 nm and 3.28 eV. The electrical and optical properties of the obtained $SrCu_2O_2$ thin films deposited by RF magnetron sputtering were compared with those deposited by PLD and e-beam.

SnO2 Nanowire Networks on a Spherical Sn Surface: Synthesis and NO2 sensing properties (구형 Sn 표면의 SnO2 나노와이어 네트워크: 합성과 NO2 감지 특성)

  • Pham, Tien Hung;Jo, Hyunil;Vu, Xuan Hien;Lee, Sang-Wook;Lee, Joon-Hyung;Kim, Jeong-Joo;Heo, Young-Woo
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2018.06a
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    • pp.142.2-142.2
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    • 2018
  • One-dimensional metal oxide nanostructures have attracted considerable research activities owing to their strong application potential as components for nanosize electronic or optoelectronic devices utilizing superior optical and electrical properties. In which, semiconducting $SnO_2$ material with wide-bandgap Eg = 3.6 eV at room temperature, is one of the attractive candidates for optoelectronic devices operating at room temperature [1, 2], gas sensor [3, 4], and transparent conducting electrodes [5]. The synthesis and gas sensing properties of semiconducting $SnO_2$ nanomaterials have become one of important research issues since the first synthesis of SnO2 nanowires. In this study, $SnO_2$ nanowire networks were synthesized on a basis of a two-step process. In step 1, Sn spheres (30-800 nm in diameter) embedded in $SiO_2$ on a Si substrate was synthesized by a chemical vapor deposition method at $700^{\circ}C$. In step 2, using the source of these Sn spheres, $SnO_2$ nanowire (20-40 nm in diameter; $1-10{\mu}m$ in length) networks on a spherical Sn surface were synthesized by a thermal oxidation method at $800^{\circ}C$. The Au layers were pre-deposited on the surface of Sn spherical and subsequently oxidized Sn surface of Sn spherical formed SnO2 nanowires networks. Field emission scanning electron microscopy and high-resolution transmission electron microscopy images indicated that $SnO_2$ nanowires are single crystalline. In addition, the $SnO_2$ nanowire is also a tetragonal rutile, with the preferred growth directions along [100] and a lattice spacing of 0.237 nm. Subsequently, the $NO_2$ sensing properties of the $SnO_2$ network nanowires sensor at an operating temperature of $50-250^{\circ}C$ were examined, and showed a reversible response to $NO_2$ at various $NO_2$ concentrations. Finally, details of the growth mechanism and formation of Sn spheres and $SnO_2$ nanowire networks are also discussed.

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Microstructure analyses of aluminum nitride (AlN) using transmission electron microscopy (TEM) and electron back-scattered diffraction (EBSD) (투과전자현미경과 전자후방산란회절을 이용한 AlN의 미세구조 분석)

  • Joo, Young Jun;Park, Cheong Ho;Jeong, Joo Jin;Kang, Seung Min;Ryu, Gil Yeol;Kang, Sung;Kim, Cheol Jin
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.25 no.4
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    • pp.127-134
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    • 2015
  • Aluminum nitride (AlN) single crystals have attracted much attention for a next-generation semiconductor application because of wide bandgap (6.2 eV), high thermal conductivity ($285W/m{\cdot}K$), high electrical resistivity (${\geq}10^{14}{\Omega}{\cdot}cm$), and high mechanical strength. The bulk AlN single crystals or thin film templates have been mainly grown by PVT (sublimation) method, flux method, solution growth method, and hydride vapor phase epitaxy (HVPE) method. Since AlN suffers difficulty in commercialization due to the defects that occur during single crystal growth, crystalline quality improvement via defects analyses is necessary. Etch pit density (EPD) analysis showed that the growth misorientations and the defects in the AlN surface exist. Transmission electron microscopy (TEM) and electron back-scattered diffraction (EBSD) analyses were employed to investigate the overall crystalline quality and various kinds of defects. TEM studies show that the morphology of the AlN is clearly influenced by stacking fault, dislocation, second phase, etc. In addition EBSD analysis also showed that the zinc blende polymorph of AlN exists as a growth defects resulting in dislocation initiator.

Characterization of SiC nanowire synthesize by Thermal CVD

  • Jeong, Min-Uk;Kim, Min-Guk;Song, U-Seok;Jeong, Dae-Seong;Choe, Won-Cheol;Park, Jong-Yun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.74-74
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    • 2010
  • One-dimensional nanosturctures such as nanowires and nanotube have been mainly proposed as important components of nano-electronic devices and are expected to play an integral part in design and construction of these devices. Silicon carbide(SiC) is one of a promising wide bandgap semiconductor that exhibits extraordinary properties, such as higher thermal conductivity, mechanical and chemical stability than silicon. Therefore, the synthesis of SiC-based nanowires(NWs) open a possibility for developing a potential application in nano-electronic devices which have to work under harsh environment. In this study, one-dimensional nanowires(NWs) of cubic phase silicon carbide($\beta$-SiC) were efficiently produced by thermal chemical vapor deposition(T-CVD) synthesis of mixtures containing Si powders and hydrocarbon in a alumina boat about $T\;=\;1400^{\circ}C$ SEM images are shown that the temperature below $1300^{\circ}C$ is not enough to synthesis the SiC NWs due to insufficient thermal energy for melting of Si Powder and decomposition of methane gas. However, the SiC NWs are produced over $1300^{\circ}C$ and the most efficient temperature for growth of SiC NWs is about $1400^{\circ}C$ with an average diameter range between 50 ~ 150 nm. Raman spectra revealed the crystal form of the synthesized SiC NWs is a cubic phase. Two distinct peaks at 795 and $970\;cm^{-1}$ over $1400^{\circ}C$ represent the TO and LO mode of the bulk $\beta$-SiC, respectively. In XRD spectra, this result was also verified with the strongest (111) peaks at $2{\theta}=35.7^{\circ}$, which is very close to (111) plane peak position of 3C-SiC over $1400 ^{\circ}C$ TEM images are represented to two typical $\beta$-SiC NWs structures. One is shown the defect-free $\beta$-SiC nanowire with a (111) interplane distance with 0.25 nm, and the other is the stacking-faulted $\beta$-SiC nanowire. Two SiC nanowires are covered with $SiO_2$ layer with a thickness of less 2 nm. Moreover, by changing the flow rate of methane gas, the 300 sccm is the optimal condition for synthesis of a large amount of $\beta$-SiC NWs.

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A Study on Improved Open-Circuit Voltage Characteristics Through Bi-Layer Structure in Heterojunction Solar Cells (이종접합 태양전지에서의 Bi-Layer 구조를 통한 향상된 개방전압특성에 대한 고찰)

  • Kim, Hongrae;Jeong, Sungjin;Cho, Jaewoong;Kim, Sungheon;Han, Seungyong;Dhungel, Suresh Kumar;Yi, Junsin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.35 no.6
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    • pp.603-609
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    • 2022
  • Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I1) and the next one a-SiOx:H(I2) were used, where a-SiOx:H(I2) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I1). Using a-SiOx:H as I2 layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiOx:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiOx:H microstructure can help the carrier transportation through tunneling and thermal emission.