• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Journal of the Korea Society for Simulation
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• v.11 no.1
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• pp.23-30
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• 2002

An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1] In this paper we fabricated N, P-MOSFEET tall analyse hump characteristics in various rounding oxdation thickness(ex : Skip, 500, 800, 1000$\AA$). As a result we found that hump occurred at STI channel edge region by field oxide recess. and boron segregation(early turn on due to boron segregatiorn at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess( 20nm), wet oxidation etch time(19HF,30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and fate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• Transactions of Materials Processing
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• v.13 no.4
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• Bulletin of the Korean Chemical Society
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• v.24 no.11
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• pp.1613-1617
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• 2003

In the phosphoric acid based etchant, the dissolution rates of Mo films were measured by microgravimetry and the corrosion potentials of Mo and Al were estimated by Tafel plot method with various concentrations of nitric acid. Dissolution rate of Mo increased with the nitric acid concentration and reached a limiting value at high concentration of nitric acid in ambient condition. Corrosion potentials of Mo and Al shifted to positive direction and the difference between potentials of both metals was about 1,100 mV and 1,200 mV with 1% and above 4% of $HNO_3$, respectively. For a Mo/Al bilayers, the dissolution rate inversion is the main reason for good taper angle in shower etching process. Taper angles are observed by scanning electron microscope (SEM) after wet etching process for Mo/Al layered films with different concentrations of $HNO_3$. In the etch side profile, it was found that Al corroded faster than Mo below 4% of $HNO_3$ in dip etching process, however, Mo corroded faster above 4%. Trend for variation of taper angle of etched side of Mo/Al layered film can be explained by considering the effect corrosion rates of both metals with various concentrations of $HNO_3$.

• Current Applied Physics
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• v.18 no.11
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• pp.1436-1440
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• 2018

SiN and SiCN film production using plasma-enhanced atomic layer deposition (PE-ALD) is investigated in this study. A developed high-power and high-density multiple inductively coupled plasma (multi-ICP) source is used for a low temperature PE-ALD process. High plasma density and good uniformity are obtained by high power $N_2$ plasma discharge. Silicon nitride films are deposited on a 300-mm wafer using the PE-ALD method at low temperature. To analyze the quality of the SiN and SiCN films, the wet etch rate, refractive index, and growth rate of the thin films are measured. Experiments are performed by changing the applied power and the process temperature ($300-500^{\circ}C$).

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.47.2-47.2
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• 2010

For reducing outer reflection in mono-crystalline silicon solar cell, wet texturing process has been adapted for long period of time. Nowadays mixed solution with potassium hydroxide and isopropyl alcohol is used in silicon surface texturing by most manufacturers. In the process of silicon texturing, etch rate is very critical for effective texturing. Several parameters influence the result of texturing. Most of all, temperature, process time and concentration of potassium hydroxide can be classified as important factors. In this paper, temperature, process time and concentration of potassium hydroxide were set as major parameters and 3-level test matrix was created by using robust design for the optimized condition. The process optimization in terms of lowest reflection and stable etch rate can be traced by using robust design method.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.81-86
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• 2004

A new method to improve the wet etching characteristics is described. The anisotropic wet-etching of (100) Si with megasonic wave has been studied in KOH solution. Etching characteristics of p-type (100) 6 inch Si have been explored with and without megasonic irradiation. It has been observed that megasonic irradiation improves the characteristics of wet etching such as an etch uniformity and surface roughness. The etching uniformity on the whole wafer with and without megasonic irradiation were less than ${\pm}1\%$ and more than $20\%$, respectively. The initial root-mean-square roughness($R_{rms}$) of single crystal silicon is 0.23 nm. It has been reported that the roughnesses with magnetic stirring and ultrasonic agitation were 566 nm and 66 nm, respectively. Comparing with the results, etching with megasonic irradiation achieved the Rrms of 1.7 nm on the surface after the $37{\mu}m$ of etching depth. Wet etching of silicon with megasonic irradiation can maintain nearly the original surface roughness after etching process. The results have verified that the megasonic irradiation is an effective way to improve the etching characteristics such as etch uniformity and surface roughness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.325-331
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• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.351-354
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• 2004

This work presents a simple and cost-effective approach for maskless fabrication of positive-tone silicon master for the replica molding of hyperfine elastomeric channel. Positive-tone silicon masters were fabricated by a maskless fabrication technique using the combination of nanoscratch by Nanoindenter ⓡ XP and XOH wet etching. Grooves were machined on a silicon surface coated with native oxide by ductile-regime nanoscratch, and they were etched in a 20 wt％ KOH solution. After the KOH etching process, positive-tone structures resulted because of the etch-mask effect of the amorphous oxide layer generated by nanoscratch. The size and shape of the positive-tone structures were controlled by varying the etching time (5, 15, 18, 20, 25, 30 min) and the normal loads (1, 5 mN) during nanoscratch. Moreover, the effects of the Berkovich tip alignment (0, 45$^{\circ}$) on the deformation behavior and etching characteristic of silicon material were investigated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.2
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• pp.60-69
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• 1998

Polysilicon surface mdoification tecnique is developed to reduce the sticking of microstructures fabricated by micromachining. Modified anti-sticking grain holes are simply formed by two-step dry eth without additional photolithography nor deposition of thin films. Both process-induced sticking and in-use sticking are successfully reduced more than two times by adopting grain holed polysilicon substrate. A sticking model for cantilever beam is derived. This model includes bending moment stems from stress gradient along the thickness directionof structural polysilicon. Because the surface tension of rinse liquid and the surface energy of the solids to be stuk tend to decrease in recently developed anti-sticking techniques, the effect of stress gradient will play an important role to analyze the sticking phenomena. Effect of the temperature during post-release rinse and dry is modelled and verified experimentally. Based on developed anti-sticking polysilicon structure and the sticking model, sticking of microstructure, fabricated by simple wet process including sacrificial layer etch and rinse with deionized water without special equimpment for post-release rinse and dry was alleviated more than 3.5 times.